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Translation Examples

To show you how Verilog2VHDL works, we translated a number of Verilog designs into VHDL. The designs range from very simple to rather complex.

The designs are:

• a negedge DFF with asynchronous reset and the translation
• a module to compute the factorial and the translation
• an 8-bit equality comparator and the translation
• a one-hot counter and the translation
• a shift counter and the translation
• an 8:4 fifo and the translation
• an IEEE1149.1 TAP controller and the translation
• a cache coherency protocol and the translation

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