SynaptiCAD Online Tutorials

Timing Diagram Editing Tutorials

Basic Drawing and Timing Analysis Tutorial demonstrates the basic timing diagram editor features. It teaches you how to draw timing diagrams using delays, setups, clocks and part libraries and how to use timing diagrams to help detect timing errors in digital designs. It also covers the waveform editing features, measurement and quick access buttons.

The Simulated Signals Tutorial demonstrates how Simulated Signals reduce the amount of time needed to draw and update a timing diagram, because the waveform is described using a Boolean or registered logic equation. With Simulated Signals you will no longer have to figure the output of a combinational circuit or calculate the critical path of a synchronous circuit by hand. WaveFormer Pro has an internal interactive simulator that supports multi-bit equations with true min-max timing, unlike traditional simulators that can only represent single-valued delays. This tutorial contains some simple examples of Boolean and registered logic equations that showcase the simulator's capabilities.

The Display and Documentation Tutorial introduces techniques for controlling the display of parameters, clocks, waveforms, markers and text objects. These techniques will allow you to control exactly what your timing diagrams look like and what information is displayed.

The Analog Signals Tutorial demonstrates how to easily create and display analog waveforms with the mouse, and generating with waveform and label equations.

Parameter Libraries explains how to create and use timing parameter libraries. Library files contain the timing parameter information for circuit components.The timing diagram editor can be used to create libraries with parameters that are exclusive to your projects. The timing diagram editor also ships with several standard libraries that contain over 10,000 timing parameters, and it also supports the industry standard TDML on-line component information.

The Advanced Modeling and Simulation Tutorial demonstrates how WaveFormer Pro can quickly model and simulate a digital system of moderate complexity. We will be modeling a circuit that computes histograms for 64K of data generated by a 12-bit Analog-To-Digital converter (this is a popular method for testing dynamic SNR for ADCs). This circuit is a simplified form of a real VME board that would take several months to model and simulate using conventional EDA tools. Using WaveFormer, we will model and simulate this simplified circuit in 20 minutes. The full circuit with the complete VME bus interface protocol could be modeled and debugged in about 4 hours.

Test Bench Generation Tutorials

The Advanced HDL Stimulus Generation Tutorial describes how to generate Verilog and VHDL basic stimulus test benches using WaveFormer Pro, VeriLogger, Reactive Test Bench Option, and TestBencher Pro. It explores how different waveforms and state values in a timing diagram will affect the generation of the test bench code. It also explores the SynaptiCAD language-independent signal types which allow a single timing diagram to generate both VHDL and Verilog test benches.

The Reactive TestBench Generation Tutorial demonstrates the Reactive Test Bench Generation Option which can be added to WaveFormer Pro, DataSheet Pro, VeriLogger, and BugHunter Pro. The features are included in TestBencher Pro, so it is also a good introduction to creating a single timing transaction in TestBencher Pro. With Reactive Test Bench Generation, users can draw "expected" waveforms on the MUT output ports and add "samples" to the waveforms to test for specific state values. During simulation, the code generated by the samples would watch the output from the model under test and compare it to the drawn waveform states. Samples can perform a variety of functions such as pausing the simulation to debug a problem, reporting errors and warnings, user-defined actions, and triggering other samples.

TestBencher Pro: Basic Tutorial covers the basic concepts of using TestBencher Pro to generate bus-functional models for Verilog and VHDL. It covers signal properties (type, direction, vector size, and bi-directional segments), samples, parameterized state values, end diagram markers, interface diagrams, modifying top-level template files, and generating test benches. TestBencher Pro users should do this tutorial.

TestBencher Pro: AMBA Example demonstrates how to create and use an AMBA AHB master. It makes extensive use of Pipeline Boundary Markers in the master transactors which are used to model the pipeline behavior defined by the AMBA specification. "Blocking Samples" in the master write and read transactions are used to wait for HREADY. Loop Markers in the master idle and busy transactors insert variable number of idle or busy cycles. State Variables and "Store Sampled Value As Subroutine Output" variables in the master write transactor are used to pass the read data back to the sequencer process. There is also a User-defined Class Method that determines the burst length based on a given burst code (defined by AMBA spec.). And finally the project makes use of Constrained randomization so that idle and busy transactors are applied using a random number of idle or busy cycles.

TestBencher Pro: PCI Example demonstrates how to create PCI master and PCI slave bus-functional models (BFMs) using TestBencher Pro. These are not 100% complete BFMs that can test every feature of the PCI protocol. Instead, they are just partial BFMs to help in the understanding of TestBencher Pro. Each BFM is modeled using a TBP project, which is then instantiated in another project named PCI.hpj. This an excellent example of hierarchical model design how the user can specify ports of slave and master BFMs using the Component Signals & Ports dialog. Some features used in this example include: loop markers, wait until markers, HDL code markers, state variables, simple expect samples, blocking & non-blocking samples, and user defined samples..

TestBencher Pro: Pipeline Example demonstrates how pipelined transactors can be created and how they work. To create the pipeline phases, "Pipeline Boundary" Markers were placed on each clock edge that starts and/or ends a pipeline phase. For each "Pipeline Boundary" Marker that starts a phase, a semaphore name is specified. This is done in the "Edit Marker" dialog and can be any valid identifier. To indicate the end of the last pipeline phase, you can either select "End Boundary" as the semaphore name or create an "End Diagram" marker.

TestBencher Pro: UART Example demonstrates how to design a Universal Asynchronous Receiver/Transmitter (UART) controller which is the key component in serial bus communications. The UART takes bytes of data and transmits the individual bits in a sequential fashion. At the destination, a second UART re-assembles the bits into complete bytes. This project contains three transactors: CLK_generator, WriteSerial, and ReadSerial. In this example, the WriteSerial and ReadSerial transactors communicate with each other. They send and receive serial data on a signal named UART. But, they work with parallel data at the transactor level. For example, the write transactor has an eight bit argument which it then converts to serial data. Both of these diagrams also have a parameter named "speed" which controls how many clock cycles are to be used for each bit of data.

TestBencher Pro: VME Example demonstrates how you would create bus-functional models (BFMs) for the arbiter, master, and slave VME components. It also shows one way to configure a set of slave BFM instances to respond to different address ranges. Each of these BFMs are represented by a TestBencher Pro project which are all instantiated in a top-level project named VME.hpj. This entire example is composed of unclocked diagrams.

Simulation Tutorials

Basic Verilog Simulation demonstrates the basic simulation features of the VeriLogger simulators (simx and vlogcmd) and the graphical debugger (BugHunter Pro). It teaches you how to create and manage a project and how to build, simulate, and debug your design. It also demonstrates the graphical test bench generation features that are unique to BugHunter Pro.

Optional Feature Based Tutorials

Waveform Comparison is an optional module that can be added to most of SynaptiCAD�s products that have a waveform editing window. This feature allows comparison between two timing diagrams or between individual signals in a timing diagram. The results of two simulation runs, or of logic analyzer data and a simulation run, can be compared very easily using this feature.

Gigawave and WaveViewer Viewer Tutorial covers the following topics: opening a waveform file, the differences between opening and importing a file, saving a .btim file, creating a filter file to selectively load sets of signals from a waveform file, and available licensing options for enhancing WaveViewer.

Transaction Tracker Tutorial explores semantic differences between some of the most commonly used PSL operators. The assertions in this tutorial have been kept very simple, so that it is easy to see the differences between the operators. It is important to understand these distinctions before attempting to write practical, real world assertions.

Evaluators: If you are evaluating the product we recommend that you do at least the General Design tutorials. These will give you a good idea of the flexibility of the product. If you design in VHDL or Verilog you should also look at the HDL tutorial and the TestBencher tutorial and examples.