Press Releases

News

SynaptiCAD's WaveFormer supports Agilent & Tektronix equipment and Hyperlynx

SynaptiCAD presents IO Checker 2.2, the FPGA and PCB IO verification tool

Timing Diagram Editors Simplify FPGA Synthesis

SynaptiCAD releases HDL Simulator Swapper

VHDL/Verilog Converters upgraded for Verilog 2005

VeriLogger Supports Symbolic Libraries and Runtime Optimizations

SynaptiCAD Speeds Up Free Waveform Viewer

SynaptiCAD's BugHunter Supports C++ and SystemC

TestBencher Simplifies Random Transaction Generation

SynaptiCAD's BugHunter Supports 64-bit ModelSim & Incisive Simulators

SynaptiCAD's GOF fixes Logic Equivalence Check Failures

WaveFormer Lite Generates Mixed Signal Test Benches for all FPGA design flows

VeriLogger supports encrypted models from Actel, Altera, and Xilinx

Timing Diagram Editors offer Editable Analog Equations

SynaptiCAD's 64-Bit Verilog Simulator is 30% Faster

Free High Performance Verilog 2001 simulator

Gates-on-the-Fly Netlist Editor adds Waveform Viewer Interoperability

SynaptiCAD tools import Xilinx timing information

SynaptiCAD Timing Diagram Editors support Sampled Analog Signals

Gates-on-the-Fly Netlist Editor and Schematic Viewer

SynaptiCAD offers HDL Works Tools

V2V Translators get Verilog 2001 Support and Graphical Debugger

Timing Diagram Editors add Mixed-Signal Capabilities

Free VCD Waveform Viewer Gets Faster

SynaptiCAD Acquires V2V Software and offers HDL Translation service

SynaptiCAD upgrades VeriLogger Extreme - version 12

SynaptiCAD upgrades WaveFormer Pro and DataSheet Pro - version 12

SynaptiCAD releases VeriLogger Extreme a new Verilog simulator

SynaptiCAD updates Free Waveform Viewer

SynaptiCAD celebrates 14 years of Timing Diagram Editor Development

SynaptiCAD Products Now Available for Linux

University of Washington uses SynaptiCAD's Verilog simulator, 2004 Report

SynaptiCAD and Actel Upgrade Libero IDE With Reactive Test Bench Generation

SynaptiCAD joins graphical debugging market

SynaptiCAD and Pulse Instruments Partnership

DataSheet Pro adds Multiple Timing Diagrams

SynaptiCAD releases PinPort - Hardware To Simulation Interface

SynaptiCAD Supports TestBuilder Development

TestBencher Pro generates code for OpenVera

TestBencher generates SystemC code

TestBencher Adds Support for Cycle-Based Bus Transactions

WaveFormer Pro supports Analog Signals and Waveform Comparison

OLE-Enabled DataSheet Pro Simplifies Timing Diagram Management

Articles

WWW.TESTBENCH.IN - Donna Mitchell
Test Benches can be generated from language independent timing diagrams, which are a natural way to design and display the parallel activity that occurs in within test benches.

ECN - Donna Mitchell and Dan Notestein
Writing reusable bus-functional testbench models has always been a challenge. In the past few years, several verification languages have been introduced to address that challenge. For a company like SynaptiCAD Inc. (Blacksburg, VA), which makes the TestBencher Pro graphical code generator, a diverse customer base requires that our tool be able to generate the same model in all verification languages currently in use. We have a lot of experience pushing each language to its performance limits and comparing how the languages work.

Circuit Cellar - Philip Nowe
Philip Nowe, a WaveFormer Pro user, describes the importance of timing analysis and some of the techniques and tools available for doing timing analysis. What is timing analysis? Why is timing analysis important? How do you perform timing analysis? Click here to read the paper.

ICU - Ben Rhodes and Dan Notestein
Techniques for creating Verilog, VHDL, and C++ hierarchical test benches that support re-use at different stages during the design of large-scale systems. Race avoidance, handling of multiple clock domains, lookup techniques for emulating hierarchical references to BFMs in VHDL, emulation of "class-like" data structures in Verilog and VHDL, and the use of a golden reference model to verify functionality while testing a system against constrained-random data are discussed.

ECN - Donna Mitchell
Techniques for automating the process interfacing VHDL and Verilog models to C++ high-level models. Using graphical code generation tools and public domain C++ libraries, engineers can setup a C environment and start simulating in just a few hours.

ElektronixPraxis - Donna Mitchell
German Editorial on how graphical test bench generation facilitates the collaboration of many engineers by removing the need to interpret source code. Includes both English and German translations.

Electronic Engineering Times - Richard Goering
Providing some of the first third-party tool support for the OpenVera hardware verification language, SynaptiCAD Inc. has rolled out TestBencher Pro version 7.4, which generates OpenVera testbenches from timing diagrams.

Synapticad testbench generator adds SystemC support

Electronic Engineering Times - Richard Goering
Synapticad Inc. said it is offering the first tool able to generate SystemC testbenches from language-independent timing diagrams. The company's TestBencher Pro 7.2 graphical testbench-generation tool includes support for SystemC, an emerging system-level

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