// A thumbsucked design of a one-hot counter to test translation of some of the 
// Verilog constructs: for loop, initial w/event control, relational ops

module hot_counter(powerup, hotout, reset);

input reset;
input [1:0] powerup;
output [7:0] hotout;
reg [7:0] hotout, index, init_index;

initial  @( negedge powerup[0] ) 
	for ( init_index = 0; init_index < 8; init_index = init_index + 1 )
		hotout[init_index] = 0;

always @( powerup or reset )
if ( powerup )
	for ( index = 'd 0; index <= 7; index = index + 1 )
	begin
		#10 hotout[index] = 1;
		if ( index ) hotout[index-1] = 0;
		else hotout[7] = 0;
	end
else if ( reset > 0 )
	for ( index = 0; index < 8; index = index + 1 )
		hotout[index] = 0;

endmodule