--------------------------------------------------------------------------------
--
-- File Type:    VHDL 
-- Input Verilog file was: factor.v
-- Tool Version: verilog2vhdl  v2.2  Tue May 16 16:50:46 EDT 1995  
-- Date Created: Thu May 25 09:48:42 1995
--
--------------------------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY factor IS
PORT (SIGNAL n : IN std_logic_vector(3 DOWNTO 0);
      SIGNAL result : OUT std_logic_vector(31 DOWNTO 0));
END factor;

LIBRARY Verilog;
ARCHITECTURE VeriArch OF factor IS
USE Verilog.functions.all;
USE Verilog.v2v_types.all;
SIGNAL V2V_result : std_logic_vector(31 DOWNTO 0) REGISTER ;
SIGNAL GUARD : boolean := TRUE;
FUNCTION factorial (SIGNAL operand : IN std_logic_vector(3 DOWNTO 0)) RETURN integer IS 
VARIABLE factorial : integer;
VARIABLE index : v2v_integer;
BEGIN
   factorial := to_integer(to_integer(ternary(operand, 1, 0)));
   index := 2;

   WHILE index <= operand LOOP
      factorial := to_integer(index * factorial);
      index := index + 1;
   END LOOP;

   RETURN factorial;
END;
BEGIN

PROCESS 
BEGIN
   WAIT ON n;
   V2V_result <= to_stdlogicvector(factorial(n), 32);
   WAIT FOR 0 NS;
END PROCESS;
result <= V2V_result;
END VeriArch;