v2vh_dff.v

//Negedge DFF with asynchronous reset

`timescale 10 ns/100 ps

module dff(D, clk, Q, set, le);

input D, clk, set, le;
output Q;
reg Q;
wire d_in;

parameter 
	delay_typ = 1, delay_max = 2;

// behavioral input mux
assign #(1 : delay_typ : delay_max) d_in = (D & le) | (Q & ~le);

always @(negedge clk or posedge set)
    if ( set == 1 )
	Q = 1;
    else
	Q = #1 d_in;

endmodule

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