v2vh_counter.hdl

--------------------------------------------------------------------------------
--
-- File Type:    VHDL 
-- Input Verilog file was: counter.v
-- Tool Version: verilog2vhdl  v2.2  Tue May 16 16:50:46 EDT 1995  
-- Date Created: Thu May 25 09:47:11 1995
--
--------------------------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY counter IS
GENERIC (CONSTANT datapath_width : integer := 15);
PORT (SIGNAL clk : IN std_logic;
      SIGNAL strb : IN std_logic;
      SIGNAL con : IN std_logic_vector(1 DOWNTO 0);
      SIGNAL data : IN std_logic_vector(datapath_width DOWNTO 0);
      SIGNAL cnt : OUT std_logic_vector(datapath_width DOWNTO 0));
END counter;

LIBRARY Verilog;
ARCHITECTURE VeriArch OF counter IS
USE Verilog.functions.all;
USE Verilog.timing.all;
SIGNAL V2V_cnt : std_logic_vector(datapath_width DOWNTO 0) REGISTER ;
SIGNAL lim : std_logic_vector(datapath_width DOWNTO 0) REGISTER ;
SIGNAL index : std_logic_vector(datapath_width DOWNTO 0) REGISTER ;
SIGNAL consig : std_logic_vector(3 DOWNTO 0) REGISTER ;
SIGNAL enit : std_logic REGISTER ;
SIGNAL renit : std_logic REGISTER ;
SIGNAL cnte : std_logic REGISTER  := '0';
SIGNAL en : std_logic REGISTER ;
SIGNAL GUARD : boolean := TRUE;
BEGIN

PROCESS 
BEGIN
   WAIT FOR 0 NS;
   WAIT;
END PROCESS;

PROCESS 
BEGIN
   enit <= NULL;
   WAIT UNTIL posedge(strb);
   CASE con IS
      WHEN (B"00") =>
      consig <= "0001";
      WAIT FOR 0 NS;
      WHEN (B"01") =>
      consig <= "0010";
      WAIT FOR 0 NS;
      WHEN (B"10") =>
      consig <= "0100";
      WAIT FOR 0 NS;
      enit <= '1';
      WAIT FOR 0 NS;
      enit <= NULL;
      WHEN (B"11") =>
      consig <= X"8";
      WAIT FOR 0 NS;
      enit <= '1';
      WAIT FOR 0 NS;
      enit <= NULL;
      WHEN OTHERS =>
      NULL;
   END CASE;
END PROCESS;

PROCESS 
BEGIN
   enit <= NULL;
   WAIT UNTIL posedge(renit);
   enit <= '0';
   WAIT FOR 0 NS;
   enit <= NULL;
END PROCESS;

PROCESS 
BEGIN
   WAIT UNTIL negedge(strb);
   IF consig = (X"2") THEN
      lim <= data;
      WAIT FOR 0 NS;
   END IF;
END PROCESS;

PROCESS 
BEGIN
   V2V_cnt <= NULL;
   WAIT UNTIL posedge(consig(0));
   V2V_cnt <= "0000000000000001";
   WAIT FOR 0 NS;
   V2V_cnt <= NULL;
END PROCESS;

PROCESS 
BEGIN
   WAIT ON en;
   IF to_bit(en) /= '0' THEN
      cnte <= '1';
      WAIT FOR 0 NS;
   ELSE
      cnte <= '0';
      WAIT FOR 0 NS;
   END IF;
END PROCESS;

PROCESS 
BEGIN
   V2V_cnt <= NULL;
   WAIT UNTIL posedge(clk);
   IF to_bit(cnte) /= '0' THEN
      IF consig = (B"0100") THEN
         V2V_cnt <= V2V_cnt SLL 1;
         WAIT FOR 0 NS;
         V2V_cnt <= NULL;
      ELSE
         IF consig = (B"1000") AND V2V_cnt /= (B"0000000000000001") THEN
            V2V_cnt <= V2V_cnt SRL 1;
            WAIT FOR 0 NS;
            V2V_cnt <= NULL;
         END IF;
      END IF;
   END IF;
END PROCESS;

PROCESS 
BEGIN
   en <= NULL;
   WAIT ON enit;
   IF to_bit(enit) /= '0' THEN
      en <= '1';
      WAIT FOR 0 NS;
      en <= NULL;
      renit <= '1';
      WAIT FOR 0 NS;
   ELSE
      renit <= '0';
      WAIT FOR 0 NS;
   END IF;
END PROCESS;

PROCESS 
BEGIN
   en <= NULL;
   WAIT ON enit, V2V_cnt;
   IF en = '1' AND V2V_cnt = lim THEN
      en <= '0';
      WAIT FOR 0 NS;
      en <= NULL;
   END IF;
END PROCESS;
cnt <= V2V_cnt;
END VeriArch;