v2vh_bigfifo.hdl

--------------------------------------------------------------------------------
--
-- File Type:    VHDL 
-- Input Verilog file was: bigfifo.v
-- Tool Version: verilog2vhdl  v2.2  Tue May 16 16:50:46 EDT 1995  
-- Date Created: Thu May 25 09:49:24 1995
--
--------------------------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY bigfifo IS
GENERIC (CONSTANT word_length : integer := 8;
         CONSTANT mem_size : integer := 4);
PORT (SIGNAL Q0 : OUT std_logic_vector(7 DOWNTO 0);
      SIGNAL Q1 : OUT std_logic_vector(7 DOWNTO 0);
      SIGNAL Q2 : OUT std_logic_vector(7 DOWNTO 0);
      SIGNAL Q3 : OUT std_logic_vector(7 DOWNTO 0);
      SIGNAL Q0_en_i : IN std_logic;
      SIGNAL Q0_en_o : OUT std_logic;
      SIGNAL Q1_en_i : IN std_logic;
      SIGNAL Q1_en_o : OUT std_logic;
      SIGNAL pad_in : INOUT std_logic_vector(3 DOWNTO 0) BUS;
      SIGNAL pad_en_i : IN std_logic;
      SIGNAL pad_en_o : OUT std_logic;
      SIGNAL pad_in1 : INOUT std_logic BUS;
      SIGNAL pad_in2 : INOUT std_logic BUS;
      SIGNAL pad_in3 : INOUT std_logic BUS;
      SIGNAL pad_en_i1 : IN std_logic;
      SIGNAL pad_en_o1 : OUT std_logic;
      SIGNAL pad_in4 : INOUT std_logic BUS;
      SIGNAL pad_en_i2 : IN std_logic;
      SIGNAL pad_en_o2 : OUT std_logic;
      SIGNAL clk : IN std_logic);
END bigfifo;

LIBRARY Verilog;
ARCHITECTURE VeriArch OF bigfifo IS
USE Verilog.functions.all;
USE Verilog.timing.all;
USE Verilog.v2v_types.all;
TYPE MEMORY_0 IS ARRAY (0 TO mem_size - 1) OF std_logic_vector(word_length - 1 DOWNTO 0);
SIGNAL V2V_Q0 : std_logic_vector(7 DOWNTO 0);
SIGNAL V2V_Q1 : std_logic_vector(7 DOWNTO 0);
SIGNAL V2V_Q2 : std_logic_vector(7 DOWNTO 0);
SIGNAL V2V_Q3 : std_logic_vector(7 DOWNTO 0);
SIGNAL V2V_Q0_en_o : std_logic;
SIGNAL V2V_Q1_en_o : std_logic;
SIGNAL V2V_pad_en_o : std_logic;
SIGNAL V2V_pad_en_o1 : std_logic;
SIGNAL V2V_pad_en_o2 : std_logic;
SIGNAL mem : MEMORY_0 REGISTER ;
SIGNAL i : v2v_integer REGISTER ;
SIGNAL pad_out : std_logic_vector(3 DOWNTO 0) REGISTER ;
SIGNAL s_in : std_logic_vector(3 DOWNTO 0) REGISTER ;
SIGNAL pad_out1 : std_logic REGISTER ;
SIGNAL pad_out2 : std_logic REGISTER ;
SIGNAL pad_out3 : std_logic REGISTER ;
SIGNAL pad_out4 : std_logic REGISTER ;
SIGNAL s_in1 : std_logic REGISTER ;
SIGNAL s_in2 : std_logic REGISTER ;
SIGNAL s_in3 : std_logic REGISTER ;
SIGNAL s_in4 : std_logic REGISTER ;
SIGNAL GUARD : boolean := TRUE;
BEGIN

PROCESS 
BEGIN
   WAIT UNTIL posedge(clk);
   i <= mem_size;
   WAIT FOR 0 NS;

   WHILE i > 1 LOOP
      mem(i - 1) <= mem(i - 2);
      WAIT FOR 0 NS;
      i <= i - 1;
      WAIT FOR 0 NS;
   END LOOP;

   mem(0) <= s_in4 & s_in3 & s_in2 & s_in1 & s_in;
   WAIT FOR 0 NS;
END PROCESS;

PROCESS 
BEGIN
   WAIT ON pad_en_i, pad_in, V2V_Q3;
   IF pad_en_i = '1' THEN
      s_in <= pad_in;
      WAIT FOR 0 NS;
      pad_out <= "ZZZZ";
   ELSE
      pad_out <= V2V_Q3(3 DOWNTO 0);
      WAIT FOR 0 NS;
      s_in <= "ZZZZ";
      WAIT FOR 0 NS;
   END IF;
END PROCESS;

PROCESS 
BEGIN
   WAIT ON pad_en_i1, pad_in1, pad_in2, pad_in3, V2V_Q3;
   IF pad_en_i1 = '0' THEN
      s_in1 <= pad_in1;
      WAIT FOR 0 NS;
      s_in2 <= pad_in2;
      WAIT FOR 0 NS;
      s_in3 <= pad_in3;
      WAIT FOR 0 NS;
      pad_out1 <= 'Z';
      WAIT FOR 0 NS;
      pad_out2 <= 'Z';
      WAIT FOR 0 NS;
      pad_out3 <= 'Z';
      WAIT FOR 0 NS;
   ELSE
      s_in1 <= 'Z';
      WAIT FOR 0 NS;
      s_in2 <= 'Z';
      WAIT FOR 0 NS;
      s_in3 <= 'Z';
      WAIT FOR 0 NS;
      pad_out1 <= V2V_Q3(4);
      WAIT FOR 0 NS;
      pad_out2 <= V2V_Q3(5);
      WAIT FOR 0 NS;
      pad_out3 <= V2V_Q3(6);
      WAIT FOR 0 NS;
   END IF;
END PROCESS;

PROCESS 
BEGIN
   WAIT ON pad_en_i2, pad_in4, V2V_Q3(7);
   IF pad_en_i2 = '1' THEN
      s_in4 <= pad_in4;
      WAIT FOR 0 NS;
      pad_out4 <= 'Z';
      WAIT FOR 0 NS;
   ELSE
      pad_out4 <= V2V_Q3(7);
      WAIT FOR 0 NS;
      s_in4 <= 'Z';
      WAIT FOR 0 NS;
   END IF;
END PROCESS;
V2V_Q0_en_o <= Q0_en_i;
V2V_Q1_en_o <= Q1_en_i;
V2V_pad_en_o <= pad_en_i;
V2V_pad_en_o1 <= pad_en_i1;
V2V_pad_en_o2 <= pad_en_i2;
V2V_Q3 <= mem(3);
V2V_Q2 <= mem(2);
V2V_Q1 <= to_stdlogicvector(ternary(Q1_en_i = '0', "ZZZZZZZZ", mem(1)), 8);
V2V_Q0 <= to_stdlogicvector(ternary(Q0_en_i = '1', "ZZZZZZZZ", mem(0)), 8);
pad_in <= GUARDED pad_out;
pad_in1 <= GUARDED pad_out1;
pad_in2 <= GUARDED pad_out2;
pad_in3 <= GUARDED pad_out3;
pad_in4 <= GUARDED pad_out4;
pad_en_o2 <= V2V_pad_en_o2;
Q0 <= V2V_Q0;
Q1 <= V2V_Q1;
Q2 <= V2V_Q2;
Q3 <= V2V_Q3;
Q0_en_o <= V2V_Q0_en_o;
Q1_en_o <= V2V_Q1_en_o;
pad_en_o <= V2V_pad_en_o;
pad_en_o1 <= V2V_pad_en_o1;
END VeriArch;