v2vh_bigfifo.v


// A model of an 8:4 fifo with a 4-bit vector and 4 scalar bidirectional
// ports, and 8-bit tri-state busses to access each of the fifo registers.

module bigfifo (Q0, Q1, Q2, Q3, Q0_en_i, Q0_en_o, Q1_en_i, Q1_en_o, pad_in,  pad_en_i, pad_en_o, pad_in1,
                pad_in2, pad_in3, pad_en_i1, pad_en_o1, pad_in4, pad_en_i2, pad_en_o2, clk);

  parameter word_length = 8,
	    mem_size = 4;

  output [7:0] Q0, Q1, Q2, Q3;  //data taps

  inout [3:0] pad_in; 
  wire [3:0] pad_in; 

  inout pad_in1, pad_in2, pad_in3, pad_in4; 
  wire pad_in1, pad_in2, pad_in3, pad_in4; 

  input Q0_en_i, Q1_en_i, pad_en_i, pad_en_i1, pad_en_i2; //bidir enables
  output Q0_en_o, Q1_en_o, pad_en_o, pad_en_o1, pad_en_o2; //enable feedthroughs

  input clk;

  reg [word_length-1:0] mem [0:mem_size-1];

  integer i;
  reg [3:0] pad_out, s_in;
  reg pad_out1, pad_out2, pad_out3, pad_out4;
  reg s_in1, s_in2, s_in3, s_in4;
  wire [7:0] Q0, Q1, Q2, Q3;

    	assign Q0_en_o = Q0_en_i;
    	assign Q1_en_o = Q1_en_i;
    	assign pad_en_o = pad_en_i;
    	assign pad_en_o1 = pad_en_i1;
    	assign pad_en_o2 = pad_en_i2;
	assign Q3 = mem[3];
	assign Q2 = mem[2];
	assign Q1 = Q1_en_i == 0 ? 8'bz : mem[1];
	assign Q0 = Q0_en_i == 1 ? 8'bz : mem[0];

	assign pad_in = pad_out;
	assign pad_in1 = pad_out1;
	assign pad_in2 = pad_out2;
	assign pad_in3 = pad_out3;
	assign pad_in4 = pad_out4;


	always @(posedge clk)
	begin
		for ( i = mem_size; i > 1; i = i - 1 )
			mem[i-1] = mem[i-2];
		mem[0] = {s_in4, s_in3, s_in2, s_in1, s_in};
	end

	//bits 3:0
	always @(pad_en_i or pad_in or Q3[3:0])
	begin
	    if (pad_en_i==1)
	    	begin
 	    	s_in = pad_in;
	    	pad_out <= 4'bz;
	    	end
    	    else
	   	begin
	    	pad_out = Q3[3:0];
	    	s_in = 4'bz;
	    	end
	end

	//bits 6:4
	always @(pad_en_i1 or pad_in1 or pad_in2 or pad_in3 or Q3[6:4])
	begin
    	    if (pad_en_i1 == 0)
		begin
 	    	s_in1 = pad_in1;
 	    	s_in2 = pad_in2;
 	   	s_in3 = pad_in3;
	    	pad_out1 = 1'bz;
	    	pad_out2 = 1'bz;
	    	pad_out3 = 1'bz;
		end
    	    else
		begin
 	    	s_in1 = 1'bz;
 	    	s_in2 = 1'bz;
 	    	s_in3 = 1'bz;
	    	pad_out1 = Q3[4];
	    	pad_out2 = Q3[5];
	    	pad_out3 = Q3[6];
		end
	end

	//bit 7
	always @(pad_en_i2 or pad_in4 or Q3[7])
    	begin
    	    if (pad_en_i2 == 1) 
		begin
 	    	s_in4 = pad_in4;
	    	pad_out4 = 1'bz;
		end
    	    else
		begin
	    	pad_out4 = Q3[7];
	   	s_in4 = 1'bz;
		end
	end

endmodule