Next: Real Declaration, Main: Supported Constructs, Previous: Register and Net

Integer Declaration

One of the types allowed in Verilog is the Integer type. Integer types in Verilog are translated to a resolved subtype of the pre-defined integer type in VHDL.

Special Note: The resolved subtype v2v_integer, and type integer_array are declared in the v2v_types package available in the types.vhd file.

Phone: 540-953-3390 | Email: Sales Office

Home | Timing Diagram Editor | Verilog Simulator | VHDL Verilog TestBench Generator
About SynaptiCAD

COPYRIGHT 2019, SYNAPTICAD SALES, INC., ALL RIGHTS RESERVED.