SynaptiCAD, Company Page

SynaptiCAD was founded in 1992 to provide affordable, high-quality timing diagram editing tools. Since that time we have expanded our product line to include: VHDL & Verilog test bench generation, timing analysis, stimulus generation, DataBook documentation, and Verilog simulation.

We released our first product, The Timing Diagrammer, in 1994. The Timing Diagrammer offered powerful drawing and analysis features, coupled with a user-friendly interface not found in most EDA tools. The Timing Diagrammer is used around the world by thousands of engineers, from the largest corporations to the individual consultant. Because of its affordable price and generous volume discounts, many companies have standardized on The Timing Diagrammer as their preferred interface for creating and exchanging digital timing information.

Our second product, WaveFormer, was released in 1995 in response to customer requests for interoperability with products from other EDA vendors. Designers wanted to take the timing diagrams they drew when designing their system and use them as stimulus vectors to test the system during simulation. WaveFormer also offers waveform import capabilities from various hardware and software products. WaveFormer's documentation features allow simulation results to be annotated with timing parameters and text to produce a true timing diagram instead of just bare waveforms.

Our third product, TestBencher Pro (released in 1996), extends the capabilities of WaveFormer to generate self-testing, multi-diagram test benches for VHDL and Verilog and is primarily targeted for ASIC/FPGA designers. TestBencher Pro is the only test bench generator with customizable HDL output. TestBencher Pro customers have direct access to the HDL code generation routines, so users can add their own routines (or modify existing routines) to generate HDL code that meets their own needs.

Also in 1996, WaveFormer Pro v3.0 with Boolean equation simulation was released. With WaveFormer Pro, designers can enter Boolean equations that describe their design and immediately assess the impact of modifying logic, state and timing information without having to change a schematic or create simulator models. The Boolean simulator includes support for propagation and interconnect delays allowing any combinatorial logic to be modeled. This feature combined with its timing analysis features makes WaveFormer Pro a true rapid-prototyping environment, allowing users to ask and answer .what-if. questions before they have even created a schematic.

In 1997, WaveFormer Pro v4.0 was released with the new HDL-Based Interactive Simulation (HIS) Technology developed by SynaptiCAD. The HIS engine added automatic re-simulation and HDL behavioral language support to the Boolean equation simulation features of the previous release. WaveFormer can simulate Boolean and registered logic equations with true min/max timing. These equations are entered using a point-and-click interface of our logic wizard. WaveFormer can also simulate behavioral HDL code entered directly into the program or stored in an external module. WaveFormer Pro combines the power of a HDL simulator with the ease-of-use of a timing diagram editor.

In 1998, SynaptiCAD acquired the source code for WellSpring Solutions' VeriWell product, an IEEE-1364 compliant Verilog simulator. We combined the VeriWell simulator with SynaptiCAD's WaveFormer Pro waveform viewing environment to create VeriLogger Pro. Over 20 man years have been invested in this new type of Verilog simulation environment, which combines all the features of a traditional Verilog simulator with the most powerful graphical test vector generator on the planet. Model testing is so fast in VeriLogger Pro that you can perform true bottom-up testing of every model in your design, a critical step often skipped in the race to market.

SynaptiCAD has also been working with SI2, an industry wide standards organization, to develop the Timing Diagram Markup Language (TDML) for the exchange of interactive timing diagrams for on-line DataBooks. In November of 1996, SynaptiCAD approached SI2 and asked to be part of the ECIX program in order to develop a timing diagram format as part of the ECIX electronic data sheet standard. Subsequently, SI2 issued a Request for Technology (RFT) in Spring, 1997 to address this issue. As a result, the TDML Working Group was formed in December 1997. TDML is currently at version 1.1 and was demonstrated to at the 1999 DAC conference.

In 1999, SynaptiCAD released DataSheet Pro a TDML based editor that provides the ultimate environment for documentation professionals working with multi-diagram projects. The program gives documentation professionals the means to efficiently combine diagrams from multiple engineers into one project with uniform formatting. It uses Object Linking and Embedding (OLE) to provide immediate in-place editing of timing diagrams. Other features include style sheets, view support, direct web file generation, project management, and support for the industry-standard Timing Diagram Markup Language (TDML) format. Documentation professionals will be able to receive timing diagrams produced by design engineers using any TDML-compatible product, such as WaveFormer Pro or Timing Diagrammer Pro, and embed them directly into documentation programs like FrameMaker and Word.

SynaptiCAD is a rapidly growing company. We currently have 5 products and 25 employees plus distributors in many foreign countries. SynaptiCAD is privately owned and operated.

SynaptiCAD is a founding member of the EDA ALL-STARS cooperative, an organization dedicated to distributing information about high quality, low-cost electrical engineering design tools. SynaptiCAD is also a member of the SI2 organization and is working with them to design an XML standard for transmitting timing diagrams and timing information via on-line data sheets.

SynaptiCAD is located in the town of Blacksburg in southwestern Virginia. Blacksburg is the home of BEV (Blacksburg Electronic Village), and is the most Internet-wired town in the world. In Blacksburg, even the food stores and grade school students have web pages. Blacksburg has been featured in the national news, 60 Minutes, and Reader's Digest. Blacksburg is also the home of Virginia Tech.

Corporate History