Version 10.0 Features
SynaptiCAD is proud to release version 10.0 of our product line. Version 10.0 includes the release of
a new interactive graphical debugger, BugHunter Pro, and two great new software options
- Reactive TestBench Generation and Timing Analysis.
The Reactive Test Bench Generation option is available for WaveFormer Pro, VeriLogger Pro, BugHunter
Pro and DataSheet Pro to upgrade their native "stimulus" based test bench generation. With Reactive
Test Bench Generation, the user can describe more complex test benches that will monitor the results
from the model under test (MUT) and create reports of the pass or fail status of the simulation.
- Draw "expected" waveforms on the Module Under Test (MUT) output ports
- Add Samples to the waveforms to:
- watch output during simulation & compare to drawn states
- react to test results with a variety of actions (pause simulation, report errors/warnings,
etc.)
- Markers can be used to loop over sections of the diagram, call user-written HDL
code and wait for activity from the MUT
- Create "clock-based" or "time-based" test benches.
- Delay in clock cycles or times, based on the type of test bench being created.
- Clock-based test benches allow the user to change clock frequency without changing the
diagram.
- Clock-based test benches are required when testing with high-speed "cycle-based" simulators.
- Setups and Holds generate code to perform checks during simulation
- Sensitive Edges allow you to specify signal events you want to wait on
- Ability to insert user HDL code into testbench via Includes, HDL Markers,
and User Defined Methods (i.e. tasks/functions)
- Tutorial on Reactive TestBench Generation features. This tutorial introduces some of
the reactive test bench feature set, which is included with TestBencher Pro and can be optionally added
to Waveformer Lite, Waveformer Pro, Datasheet Pro, and BugHunter Pro. The tutorial covers creating cycle-based
test benches, for-loop markers, bi-directional signals, waiting on events driven by the model under
test (MUT), and verifying the output of the MUT
The Timing Analysis Option is available for VeriLogger Pro, BugHunter Pro, and WaveFormer Lite to upgrade
the drawing environment so that delays, samples, and holds will move and monitor waveform transitions.
This option essentially changes the timing diagram editing environment so that it becomes a timing diagram
editor capable of performing critical path timing analysis.
TestBencher Pro generates test benches from graphical timing diagrams.
- Project hierarchy tree maintains expansion information when new objects are added to
the tree
- Generate Test Bench on Build Project option automatically updates test bench for
changes to timing diagrams each time the project is compiled. This is on by default, but it can be turned
off if user wants to temporarily change some of the generated source code manually or to avoid updating
the test bench on diagram changes for quicker compiling
- Added PDF documents to explain the following TestBencher Pro examples in detail: AMBA,
PCI, pipelining, uarttest, VME. These can all be found in the {SynaptiCAD Installation Directory}\install\Examples\docs
directory
TestBencher Pro includes BugHunter Pro's Graphical Debugger
- Provides better control of external simulators & compilers
- Single Step graphical debugging supported for Mentor's ModelSim VHDL and Verilog simulators,
Cadence's NC Verilog/VHDL and Verilog XL simulators, and Aldec's ActiveHDL simulators
- Simulator settings can be defined for diagram simulations independently of project simulations
- Expanded Project Simulation Properties provides better control over external tools
and also provides multiple configurations for defining options for different machines, different
simulators, and to create debug versus high speed simulations
Bus-functional Model Code Generation
- Added two new folders under each transaction diagram in the project window: Included
External to Module and Included Internal to Module. These folders allow easy access to user
included files and is linked to the Diagram Properties dialog
- Added Initial Value field for project and diagram variables
- Test Bench and Transaction Generation Features/Modifications:
- All Note and Warning messages output by TestBencher Pro during simulation
can now be enabled/disabled via two variables: EnableNoteMessages and EnableWarningMessages
- Enhanced messages generated for Sample Display Message action
- Added extended comment block at top of generated transactors that summarizes the contents
of the transactor
- Added support for multiple diagram instances in VHDL
- New Project Generation Settings options:
- Add timestamp to each file setting (useful if the generated code is versioned
& you don't want the generated file to be different just because the time is different)
- Prefix Generated Files With setting (useful for versioned code for providing keywords
to versioning system)
- Indent Size setting added - affects all generated code in the project
- New Diagram Settings options:
- Added Delay After Clock Edge option to Diagram Settings which contains two options:
Fixed and As Drawn. If "Fixed" is selected, the user can specify the fixed amount of the
delay. This affects code generated for clocked signals
- Display Applied Inputs verbose option displays the value of transaction inputs
in the simulation log file
Features/Improvements for Transaction Parameters
- New Pipeline Boundary marker type which makes the construction of pipelined transactors
much easier and automatic
- For-Loop Markers in VHDL are now implemented using while loops so that the loop
index can be declared as a shared variable and accessed anywhere in the diagram
- Added FIFO Semaphore feature. Semaphores are created in the Project's
Class Library and Variables dialog
Simulation & Library Features
- Sim Diagram (not Sim Diagram and Project) will now drive Input signals.
This allows you to test out simulated signals contained in a transactor before integrating it into the
project
- Added syncad_vhdl_lib and syncad_verilog_lib which contains a collection
of base modules that the Testbencher Pro generated code uses. This library needs to be compiled once
per installation of TestBencher Pro and is done via the Compile Syncad Libraries button in the
Options > Simulator/Compile Settings dialog. Use of these libraries helps speed up the compilation
time of individual projects
- Added new clock models for use in VHDL which are used to more accurately simulate the
clocks drawn in TestBencher Pro's transactor diagrams. These are a part of the new syncad_vhdl_lib
All new features in BugHunter Pro, WaveFormer Pro and
Timing Diagrammer Pro are in TestBencher Pro.
TestBencher Pro has Timing Analysis, Reactive TestBench
Generation and Multiple Diagram Windows built-in.
BugHunter Pro is an interactive graphical debugger for Verilog, VHDL and C++.
- Graphical Test Bench Generation for quickly testing small modules & doing bottom up testing
- Stimulus & Results diagram
- Provide stimulus for simulation
- View simulation results in a diagram format during & after simulation
- Manage TestBench interface - easily create a set of regression tests for design
- Interactive Debugging for Verilog, VHDL and C++ simulators & compilers:
- Supports all major Verilog & VHDL Simulators
- The ability to define simulator settings for diagram simulations
- Project hierarchy tree maintains expansion information when new objects are added to
tree
- Expanded Project Simulation Properties provides better control over external tools
and also provides multiple configurations for defining options for different machines, different simulators,
and to create debug versus high speed simulations
Step-by-step debugging
- Time Break Points can be set through the Breakpoint tab in the Report window
- Source Code Break Points can be set by clicking to the left of a line of source
code in an Editor window. They can also be added through the Breakpoint tab in the Report window
- Step into & over trace debugging
- Step Into with Trace button sends a message to the Simulation Log tab in the Report
window after each step. This lets you quickly inspect the command that was just executed
- Step Over button does do not step into a function or task but allows the simulation
to continue until the next line after a function or task call
- Break at Time Zero puts the simulator in an interactive mode after compile so
that you can give the simulator commands before anything happens in the simulation. It is the equivalent
of setting a breakpoint at time zero
Watching Signal & Variable Values
- Inspect Values window lets you set and inspect register and signal values. You
can also view values at previous simulation times
- Scope buttons, with the capitol S and lower case s, change the scoping level of
the values in the Inspect Values window
- View values in Editor windows by placing the mouse button over signal or variable name
in the code
VeriLogger Pro is a Verilog simulator with built-in graphical test bench generation.
All the new WaveFormer Pro and BugHunter Pro features are also
in VeriLogger Pro (with the exception of built-in software options).
DataSheet Pro provides documentation professionals with an integrated environment for working with multiple
timing diagram documents.
All the new WaveFormer Pro and Timing Diagrammer Pro features
are also in DataSheet Pro (with the exception of built-in software options).
DataSheet Pro includes the new Timing Analysis option.
WaveFormer combines a timing diagram editor, a stimulus generator, and an interactive HDL simulator
to form a rapid prototyping EDA tool that helps you design faster with fewer mistakes.
- Added support for reading Agilent 16900 Logic Analyzer ASCII data capture (.csv)
- True incremental signal loading for VCD files
- A 2x improvement in VCD file loading
All the new Timing Diagrammer Pro features are also in WaveFormer Pro.
Timing Diagrammer Pro is a powerful, feature-laden timing diagram editor that lets you analyze your
design in the early stages, before you have a schematic.
Graphical Drawing Environment
- Ability to superimpose signals to represent "differential" signals for Group Buses by
selecting the Display as superimposed signals checkbox in the Signal Properties dialog
- Option to place white boxes under text so that text is never overwritten by other graphics
in the diagram when images are created (de-select the Transparent Text Object Background option in the
Drawing Preferences dialog
- Horizontal Justification for Text Objects - select Left, Center or Right justification
in the Edit Text dialog
- Set color of individual signal waveforms - right click signal name in Diagram Window
and select the Change Signal Color menu option
- Set line style of individual signal waveforms (e.g. dotted, dashed, etc) - right click
signal name in Diagram Window and select the Change Signal Line Type... menu option
- Speeded up Expanding bus signals into individual bits
- Speeded up drawing grids in diagrams with a large numbers of signals
Customize Parameter Window
- Change column titles for Parameter Table - double-click column name in Parameter
Window to edit name
- Set which columns are printed in Parameter Table
- right click column headers in Parameter Window to select columns
Features for Printing
- Ability to specify width of EPS images (especially ability to create larger than A
Size paper images) - use Specify Image Size and specify the Width and Height
in the Print dialog
- CUPS printing support on Unix platforms (in addition to printcaps)
General
- CORBA API that allows runtime control of application by 3rd party software
- Speeded up Find in Files function (ctrl-Shift-F) (grep tab in report window)
- Support for USB dongles (for newer laptop users which don't have parallel port)
- Faster startup on Linux, Solaris, and HPUX platforms
New Features pages for previous versions:
List of Features in Version 9.0
List of Features in Version 8.0
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