FAQ Reguarding Logic Analyzers
& Pattern Generators
Frequently Asked Questions Regarding HP Logic Analyzers and Pattern Generators
1) Can I get state/timing information from my Agilent or HP logic analyzer into an HDL simulator?
Yes. WaveFormer Pro can read HP logic analyzer files and
generate stimulus vector files for VHDL, Verilog, SPICE and other simulator formats. And for advanced
HDL users, TestBencher Pro can generate reactive VHDL/Verilog bus-functional models using Agilent or
HP logic analyzer data files.
2) Can I export my simulator data to pattern generators?
Yes. WaveFormer Pro accepts most HDL simulator files and
uses that data to produce stimulus files for Agilent and HP Pattern Generators. WaveFormer Pro
is compatible with all Verilog simulators using the standard VCD format. WaveFormer Pro can import data
from most VHDL simulators, but since there is no standard VHDL waveform format, we add brand-specific
import capabilities on a customer request basis.
3) Why would I want to use captured waveforms to drive my simulations?
You cannot look inside an FPGA/ASIC with a logic analyzer.
One of the most frustrating problems when debugging a circuit is the inability to see what’s happening
on all of the signal nodes. A logic analyzer can only show the activity on signals that are brought
out on device pins. After input and output signals are assigned, designers often use any available pins
to bring out internal signals for probing during debug. Unfortunately, many designs are I/O limited
and even when they are not, there are almost never enough pins available to bring out all the useful
internal nodes.
To combat this problem, WaveFormer contains a built-in interactive simulation engine that can simulate
registered logic equations like those used in FPGAs or CPLDs. By combining this capability with data
captured by a logic analyzer, users can find out what’s happening not only at the pins of their
devices, but also on the internal nodes that cannot be probed directly. This dramatically simplifies
the debug process, since a designer can effectively trace into his chip to determine where the problem
occurs.
4) Can I perform continuous setup and hold testing on waveforms captured with an Agilent or HP
Logic Analyzer?
Yes. WaveFormer’s simulation
environment can generate a report of all timing violations of a setup or hold time specified between
any two signals. This analysis is independent of whether it is a captured waveform or a simulated waveform.
WaveFormer’s ability to simulate internal signals makes it relatively simple to find normally elusive
setup and hold time violations between signals buried inside a chip.
5) Can I compare and analyze waveforms from different captures and simulation runs?
Yes. TestBencher Pro and
VeriLogger Pro v5.5 have the ability to compare waveforms. Users can also specify conditions under which
discrepancies can be ignored (for example, the difference time is too small to affect circuit operation).
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