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9.6 Project Generation Properties dialog

9.6 Project Generation Properties dialog

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9.6 Project Generation Properties dialog

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The top-level component of the project and each instance of a sub-project has its own set of properties that determine the way the code is generated for the component. These properties are edited through the Project Generation Properties dialog. This dialog also gives you access to the variables, parameters, and signal mappings of the Component. The controls in this dialog change depending on if you are editing a Component Instance or the actual Transaction-Level Model.

Use context menus to open Project Generation Properties dialog:

For project level properties, right-click on the Transaction-Level Model folder and choose Project Generation Properties from the context menu

For sub-project level properties, right click on a component instance (green icon) and choose Component Instance Generation Properties from the drop-down list box.

Project_properties_menus

Properties of a top-level project:

The following properties can be edited at the Transaction-Level Model level:

Enable Reference Model enables the generation of a golden reference model in C++, VHDL, or Verilog. This feature is covered in Section 9.3: Golden Reference Models.

Enable Transaction Manager enables the generation of the transaction manager code. This feature is covered in Section 7.3: Transaction Manager Overview.

Add Timestamp to Each File is useful when the generated code is versioned. Disabling this will prevent the generated file from being different just because the time is different.

Source Indent Size specifies the number of spaces that are used for indenting blocks of code.

Prefix Generated Files With edit box allows a line of text to be output at the beginning of each generated file. This is useful for noting author information or for adding keywords for version systems.

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Language and Enable TestBuilder Integration control the generation language for this component. If the language for the project is changed, then the project template file must also be changed. Section 7.8: Changing a Project Template File discusses changing the project template file.

Verbose Transaction Logging reports to the simulation  log file when transactions start and stop. Also if the transaction is applied in looping mode it reports when each loop starts.

Transaction Recording enables SDI transaction recording calls. This records every transaction that is run during simulation along with applied parameters and is written to a database that can then be imported into Cadence's SignalScan. The simulation can then be viewed as a set of transactions.

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ComponentProperties_buttons

The Signals and Ports button opens a dialog used to specify which signals will be available to external projects. It also allows you to define internal signals that are not contained in any transaction diagram.

The Classes and Variables button opens a dialog that is used to edit the classes and variables that are included in that project. See Chapter 6: Classes and Variables for more information.

The Class Methods Button opens a dialog that lets you edit the project level class methods (transaction level class methods must be edited from the transaction). See Section 6.3: Class Methods for more information.

Properties of a Component Instance of a sub-project:

Instance Name indicates which component instance is being edited and allows you can change the name of the component instance.

Checking the Edit All Instances check box indicates that changes in the properties will affect all instances of a project. If you are editing from the Transaction-Level Model folder of either the containing project or in a sub-project's Transaction-Level Model folder you will be editing all of the instances.

The Signals and Ports button opens a dialog that lets you edit how the component instance is hooked up to the containing project.

componentInstanceProperties

Disable C++ indicates whether TestBuilder is available or not.

Destination Library for TestBencher Pro Generated files:

By default, TestBencher Pro compiles the generated testbench files to the standard 'work' library in VHDL. Sometimes, however, these source files may need to be compiled to a different library. You can override the default work library destination for all generated files via a setting in the Project Generation Properties dialog.

Choose Project > Project Generation  Properties from the main menu, to open a dialog of the same name.

Type in a new destination library name into the Test Bench Destination Library box of the Project Generation Properties dialog.

prj_gen_dlg_destination_lib

 

Note: User-written source files are also compiled into the work directory by default. The destination library for each user-written source file can be set individually by right-clicking on the source file in the project window and selecting Set Destination Library For Compiled File from the context menu.