•If you are not using Libero then select Project > New Project menu and add your source code files to the list as shown in Section 4.4 Export VHDL and Verilog test benches.

•If you cannot see the WaveFormer Icon inside Libero, then you must set the Profiles to point to WaveFormer Lite. First right click and choose stimulus from context menu and select Profiles. The add a new Stimulus Profile and point it to the new Syncad.exe file.

•Follow the Actel instructions for launching WaveFormer Lite. The first time, the Actel software will create a project and hand it to WaveFormer Lite which will extract all of the signal information from the top-level ports. WaveFormer Lite will then create a timing diagram containing all of the signals (including the type, direction and size).

•If you later change the ports of the Model Under Test, you can force a signal extraction by clicking the Extract MUT Ports into Diagram button located on the program level button bar

•(Fusion Only) The export type for each analog signal needs to set according to the instructions in Section C3: Specifying Signal Types for Actel Fusing Analog Signals.

•Draw the waveforms on the signals to describe the testbench. Section 1.2 Drawing Waveforms describes how to use the mouse and the state buttons to draw waveforms.

•For clock signals, right click on the clock name and choose Signal(s) <=> Clock(s) menu to convert the signal to a SynaptiCAD clock which will draw its own waveform based on the period and frequency. Double click on the waveform to edit the clock properties. Section 2.1 Adding Clocks describes all of the clock features.

•Add Analog Waveforms using Python equations as shown in Section 8.2 Waveform Equation Blocks for editable Analog waveforms.

•(optional) Add Reactive Test Bench objects: Libero Platinum users used to receive Reactive Test Bench features with WaveFormer Lite that enabled them to generate test benches that can verify and react to output from the model under test. WaveFormer Lite with Reactive test bench generation can be purchased from SynaptiCAD directly. For more information on these capabilities, see Reactive Test Bench Manual on the Help menu. These users will be adding samples to the expected inputs to the testbench to indicate the times at which to test the values output by the model under test.

•The Extract MUT Ports into Diagram function makes a guess as to which model is the model under test and displays that model with single brackets, <>, underneath in the Models Under Test folder.

•To pick a different model under test, first right click on the MUT and choose Unset Current Model Under Test, and then right click on a different model under the User Source Files list and pick Set as Model Under Test. Multiple models under test can also be specified.

•Then press Extract MUT Ports into Diagram button to re-populate the Stimulus and Results diagram.

•Select the Export > Export Timing Diagram menu to open the file dialog, and in the save as type box choose either the VHDL w/ top level test bench or Verilog w/ top level test bench. The Top Level Test Bench types instantiates the model in the Project window and the stimulus model within a top-level model. This top-level module can then be simulated in Actel Libero without any additional setup.

•Closing this dialog generates the test bench and also displays it in the Report window so that you view the generated code.

•Section 4.4 Exporting VHDL and Verilog test benches has more information about exporting and also about adding VHDL libraries and use clauses.