Timing Diagram Editing and Analysis

Appendix C: WaveFormer Lite Help for Actel Customers

Appendix C: WaveFormer Lite Help for Actel Customers

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Appendix C: WaveFormer Lite Help for Actel Customers

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WaveFormer Lite is a special version of WaveFormer Pro that can generate VHDL and Verilog stimulus-based test benches for the Actel Libero design software and other FPGA/ASIC vendor flows. WaveFormer Lite fits seamlessly into the Actel’s design environment, automatically extracting signal information from your HDL design files, and producing HDL test bench code that can be used with any standard VHDL or Verilog simulator. WaveFormer Lite is no longer shipped by Actel as part of the Libero package, but it can be purchased from SynaptiCAD and will still work with Libero.

The latest version of WaveFormer includes a built-in project window, allowing you to create testbenches for any VHDL/Verilog design regardless of what design flow tools you use.

Section C1: WaveFormer Lite Design Flow has instructions for generating VHDL and Verilog with the Actel design environment.

Section C2: WaveFormer Lite Upgrade Options describes how to upgrade to the professional version of WaveFormer Pro. The professional version has features that help you create timing diagrams faster, analyze circuit timing, produce Data Book quality images, and translate waveform information from over 35 formats including most popular logic analyzers, pattern generators, and simulators.

Section C3: Specifying Signal Types for Actel Fusion Analog Signals describes how to set the Analog types for Fusion Analog Signals