4.3 Direct Signal Code |
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4.3 Direct Signal Code |
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4.3 Direct Signal Code |
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4.3 Direct Signal Code |
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The Verilog and VHDL tabs in the Signal Properties dialog allow you to view and edit the generated code for a specific signal.
To View or Edit the Simulated Signals Code:
•Double click on a simulated signal to open the Signal Properties dialog. The Equation Entry tab shows the settings for the simulated signal |
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•Press the Verilog or VHDL tab to open an editor window with the generated code displayed |
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•If you make changes to the generated code, they will be saved when you close the window or click to another tab. After the changes, the Equation Entry will then be disabled and a Direct Code message will be displayed in the equation box. |
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•WaveFormer Pro by default is configured to simulate Verilog code using its internal simulator. If you make direct code changes to the VHDL code, then you will also have to provide and setup a VHDL simulator as discussed in Section 4.5 HDL Code Generation Settings. |
Tips on writing direct code:
1.All the HDL code is placed inside a module. This places one important restriction on the HDL code: it cannot contain an HDL module declaration (i.e. you cannot define a new type of component inside a signal's direct HDL code block). You CAN create an instance of an HDL module, however, as long as the module is declared somewhere else (e.g. in wavelib.v). The advanced simulation tutorial covers this in more detail.
2.Signals are always treated as wires during Verilog code generation. This makes it easy to write simple continuous assignment statements. This also means that if you want to control the signal state using behavioral code, you will need to create a reg as a intermediate variable and then assign the SynaptiCAD signal to the value of the intermediate reg. This is because the values of wire (nets) cannot be set inside a behavioral (initial or always) block. For example, direct behavioral code for a signal called SIG0 that inverts whenever CLK changes state would be written as:
reg tempSIG0; //temporary reg
always @(CLK)
begin
tempSIG0 = !tempSIG0; //invert temporary whenever CLK changes
end
assign SIG0 = tempSIG0; //set WaveFormer signal to value of tempSIG0
Notice that you do not have to declare the WaveFormer signal SIG0 because WaveFormer automatically creates it. However, you do have to declare the temporary reg tempSIG0 because WaveFormer doesn't know anything about it.
