Test benches created by TestBencher can be simulated standalone in standard simulators, without requiring a TestBencher license to perform the simulation. But during development of a test bench, it's often useful to use TestBencher to launch and control your chosen HDL simulator. TestBencher can remotely control most popular 3rd-party VHDL and Verilog simulators and C++ compilers. The settings for configuring the launch of external simulators and tools are controlled using the Simulator and Compiler Settings dialog described in Step 7: Setup External Simulators.
To build and simulate a bus-functional model:
Both third-party simulators and SynaptiCAD's simulators are controlled through the simulation button bar. Below is a brief description of how to simulate a test bench using the simulation button bar. See the BugHunter Manual for complete details on HDL simulation and debugging features.
•Before simulating, it is a good idea to press the Generate Test Bench button to make sure your most recent changes have been incorporated into the generated code (See Step 6: Generate the Test Bench). |
•If this is the first time you are using TestBencher/BugHunter to simulate with your current simulator, then follow the steps in Step 7: Setup External Simulators and make sure to follow the directions for the Compile Syncad Libraries button to compile libraries using your new simulator. |
•Click the yellow Compile Model and Test Bench button. This builds (parses) the project using the tools specified in the Project Simulation Properties and Simulator/Compiler Settings dialogs (Section 8.2: Project Simulation Properties dialog). For mixed language projects like TestBuilder, several tools will be needed to compile different parts of the project. For example, TestBuilder projects require a C++ compiler and an HDL simulator. |
•In the Report window, look at the Errors tab for any compile errors. If there are errors, then fix them, regenerate the test bench, and recompile, before going on to the next step. |
•Run the Simulation. The Run/Resume button compiles the files (if there have been changes since the last build) and then runs a simulation until it is stopped by a breakpoint, the Pause button, the End Simulation button, or the end of the simulation is reached. The Run/Resume button also continues a simulation when it is currently paused. The <F5> key and the Simulate > Run menu perform the same function. Simulations can also be run in single-step mode (green buttons with multiple small arrows) or run for a specified amount of simulation time (green button with an hourglass above it) |
•During Simulation the status of the simulation is displayed in the bottom right hand corner of the TestBencher Pro main window. When the simulation is complete, Simulation Good will be displayed. |
•When a simulation is paused or completes, the following information will be displayed: •The simulation waveforms will be displayed in the Stimulus and Results diagram window. •The simulation log file is shown in the Report window. Any notes, warnings and errors reported by the simulator will appear in this log. •In the Project window, the Simulated Model folder contains the compiled MUT and the Stimulus & Results diagram. If there are any archived stimulus/results files, they will be in the Stimulus & Results Archive folder. If any extra files are necessary for TestBencher to build the project, they will be automatically added to the project, and contained in the Compiled Library Files folder. |
Using TestBencher to start the ModelSim Graphical Interface
In addition to being able to launch the command line ModelSim simulators, TestBencher can also launch the graphical version of ModelSim. Once a design is loaded into ModelSim, three windows will be opened automatically - the Structure, Signals, and Wave windows. By default, TestBencher will also add all of the top-level signals from the component entity to the Wave window. These signals will allow you to monitor the MUT and the transactions during simulation from inside the ModelSim interface.