2.6 Sensitive Edges - a Blocking Construct

An input signal can be set to have sensitive edges, so that the test bench will wait on every falling or rising edge that the model under test generates. The sensitive edge controls are located in a signal's Signal Properties dialog. A signal with sensitive edges will be drawn with arrows on the sensitive edges. This sequence recognition is limited to single bit signals.

Alternatives to Sensitive Edges

With Sensitive edges, there is no time-out feature, so the testbench can potentially hang if the model under test does not provide the edges as drawn. There are two other blocking constructs, samples and markers, that provide methods of waiting that are less demanding than the sensitive edge construct. See Section 3.3: Samples that Block Clock Domains and Section 5.4 Wait Until Markers for complete details on using these constructs to wait for events. Also, Section 10.2 Waiting for Signal Transitions or Conditions has an example using all three blocking features.

Enable sensitive edges on a signal:

•Double-click the name of the signal to open the Signal Properties dialog.

•Check either Rising Edge Sensitive or Falling Edge Sensitive or both to indicate the blocking points for the testbench.

sensitive_edge_control

•Press the OK button to close the Signal Properties dialog. Notice the waveform edges now have arrows on the sensitive edges

sensitive_edge_waveform

The code generation for sensitive edges looks like the following:

VHDL:

-- Sensitive Falling Edge on signal: TRDY

wait until falling_edge(TRDY) or (tb_DgmAborted);

Verilog:

// Sensitive Falling Edge on signal: TRDY

@(negedge TRDY);