8.3 Compiling and Simulating VHDL Output

The VHDL produced by Verilog2VHDL needs to be run through a VHDL simulation and/or synthesis tool. This chapter describes the compilation order for the VHDL files, followed by some examples illustrating the concept.

Compiling Original and Translated Code Using BugHunter

If you're using BugHunter to compile your code, it's frequently useful to create two compile configurations in your project (one for compiling the original source code, and one for the translated source code). You can set the Compile Source Files Of Type check boxes in the General tab of the Project Simulation Properties dialog so that one configuration only compiles Verilog files and the other configuration only compiles VHDL files (See Section 2.1 Project Simulation Properties).

Compiling Verilog2VHDL packages

In order to facilitate translation, SynaptiCAD provides several VHDL packages along with the tool. Often times these packages are used in translated files. User must compile these packages into a VHDL library called ASC before compiling the translated files.

If the translated output VHDL files do not use any of these packages, then there is no need to compile any of the packages supplied with Verilog2VHDL. You can directly proceed to compiling the VHDL output file in this case.

Compiling Verilog2VHDL packages inside BugHunter

It's extremely easy to compile the Verilog2VHDL packages if you use the BugHunter GUI to launch your simulator. All you need to do is press the Compile Syncad Libraries button in the Simulator and Compiler Settings dialog as shown in Step 1: Setup the Simulator Path.

Location of Verilog2VHDL packages

In the ensuing discussion, v2v_location will be used to denote the location of the translation software on the host machine. When v2v is installed via the SynaptiCAD tool suite installer (i.e.allproducts.exe), the translation software is placed in a subdirectory of the main installation directory called v2v. For example, on Windows this directory will typically be c:\SynaptiCAD\v2v and on Unix this directory will typically be /usr/local/synapticad-version/v2v. The phrase vhdl_sim will be used to refer to the user's VHDL compiler.

Verilog2VHDL comes with the following packages: timing, buffers, numeric_std, v2v_types, utils and functions. The timing package resides in the location v2v_location/lib/timing. vhd , buffers package in v2v_location/lib/buffers. vhd , numeric_std package in v2v_location/lib/numeric_std.vhd, v2v_types package in v2v_location/lib/types.vhd, utils package in v2v_location/lib/utils.vhd and the functions package in v2v_location/lib/functions.vhd. (If the `-87' switch is used, the related packages files are v2v_location/lib/numeric_std_87.vhd for the numeric_std package and v2v_location/lib/functions_87. vhd for the functions package.)

Order of Compilation for Verilog2VHDL Packages

Verilog2VHDL uses tool-specific packages to perform the translation. In the output VHDL, these packages are compiled into a VHDL logical library called ASC. The user needs to map the physical location of the compiled packages to this logical library by using VHDL compiler specific commands. Please refer to your VHDL simulator manual for tool-specific information on library mapping. Additionally, for using IEEE STD 1076-1993 compliant VHDL, some VHDL compilers need extra command-line switches.

As a representative example of the steps needed to create an ASC library using ModelSim VHDL or Active VHDL, you would need to perform the following commands:

1) cd v2v_location\v2v

If this is a read-only directory, you should first copy this directory to a location where you have write privileges and work from there instead.

2) Initialize an ASC library directory for your VHDL compiler

vlib ASC_mycompilername

3) Map this physical directory to the logical library name ASC

vmap ASC ASC_mycompilername

4) Finally, compile the packages into the newly created ASC library. The compilation order for the VHDL packages is shown below. Packages whose compile order is not important are grouped together below. vhdl_com is used as the shell invocation command for the VHDL simulator/compiler. One package is contained in each file and the filename matches the name of the package it contains (except in the case of a few packages where the filename to compile depends on whether you are using either a VHDL-87 or VHDL-93 or later compiler).

a) Compile the image_functions, timing, and buffers packages into the ASC library

% vhdl_com -work ASC image_functions.vhd

% vhdl_com -work ASC timing.vhd

% vhdl_com -work ASC buffers.vhd

b) Compile the numeric_std package into the ASC library

% vhdl_com -work ASC numeric_std.vhd OR % vhdl_com -work ASC numeric_std _87.vhd

c) Compile the v2v_types, utils, functions, and readmem packages into the ASC library

% vhdl_com -work ASC types.vhd

% vhdl_com -work ASC utils.vhd

% vhdl_com -work ASC functions.vhd OR % vhdl_com -work ASC functions_87.vhd

% vhdl_com -work ASC readmem.vhd

RTL Translation Example

Input file: example.v

/////////////////////////////////////////////////////

// dir_cell component description

/////////////////////////////////////////////////////

module dir_cell (so,shift,clock,si,idcode); output so;

input shift, idcode, si, clock;

reg cq;

wire d, shift, idcode, si, clock;

assign d = (shift & si) | (~shift & idcode); assign so = cq;

always

@(posedge clock) cq = d;

end module

Verilog2VHDL Invocation and Transcript

% v2v example.v

// UNPUBLISHED, LICENSED SOFTWARE.

// CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE

// PROPERTY OF ALTERNATIVE SYSTEM CONCEPTS OR ITS LICENSORS.

//Running..

// NOTE: Adding VHDL entity 'dir _cell' to output file

// NOTE: Adding VHDL architecture 'VeriArch'for entity 'dir _cell'

// NOTE: Adding port 'so' to entity 'dir _cell'

// NOTE: Adding port 'shift' to entity 'dir _cell'

// NOTE: Adding port 'clock' to entity 'dir _cell'

// NOTE: Adding port 'si' to entity 'dir _cell'

// NOTE: Adding port 'idcode' to entity 'dir_cell'

// NOTE: Adding Process in architecture 'VeriArch' belonging to entity 'dir _cell'

<<<<<< VHDL translation of Verilog file 'example.v'

being written to 'example . hdl' >>>>>>

Output file: example.vhd

-- File Type: VHDL

-- Tool Version: Verilog2VHDL v1.0 Mon Feb 6 16:59:45 EST 1995

-- Date Created: Mon Feb 13 15:08:29 1995

LIBRARY ieee;

USE ieee. std _logic _1164. all;

ENTITY dir_cell IS

PORT (SIGNAL so : OUT std _logic;

SIGNAL shift : IN std _logic;

SIGNAL clock : IN std _logic;

SIGNAL si : IN std _logic;

SIGNAL idcode : IN std _logic);

END dir_cell;

ARCHITECTURE VeriArch OF dir_cell IS

SIGNAL cq : std _logic REGISTER ;

SIGNAL d : std _logic;

BEGIN

d <= (shift and si) or (not shift and idcode);

so <= cq;

PROCESS

BEGIN

WAIT UNTIL posedge(clock);

cq <= d;

END PROCESS;

END VeriArch;

VHDL Compilation

% vhdl _sim example.hdl

The above command will compile the VHDL code in file example.vhd in the current directory. If it is required to compile in a separate directory, check the simulator manual for options.

Gates and Parametric Delay Example

Input File : example.v

/********************************************************************

Verilog example illustrating gate instantiations

********************************************************************* /

`timescale 1ns/10ns

module gates (q, qb, d, clk, rst); parameter delay _val=3;

output q,qb;

input d,clk,rst;

wire a,b,c,d; /*wire declarations*/

wire e,f,g,h;

nand #delay_val (qb,cf,clk,rst); /*nand gate instantiation*/

or #(1:2:3)(qb,cf,clk,rst); /*nand gate instantiation*/

xor #10 (q,a,b,e,f,g); /*xor gate*/

xor #1 (q,a,b,e,f,g); /*xor gate*/

and #2 (b,d,e,f,g); /*and gate*/

buf #4 (e,f); /*buf*/

not #4 (d,g,h); /*not gate*/

notif0 firstnot (d,g,h); /*not gate*/

end module

Verilog2VHDL Invocation and Transcript

% verilog2vhdl example.v

// Verilog2VHDL v1.0 Mon Feb 6 16:59:45 EST 1995

// Copyright (c) Alternative System Concepts Inc. 1992-1995, All
Rights Reserved.

// UNPUBLISHED, LICENSED SOFTWARE.

// CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE

// PROPERTY OF ALTERNATIVE SYSTEM CONCEPTS OR ITS LICENSORS.
//

// Running..

// NOTE: Found compiler directive 'timescale'

// NOTE: Adding VHDL entity 'gates' to output

file

// NOTE: Adding VHDL architecture 'VeriArch' for entity

'gates'

// NOTE: Adding port 'q' to entity

'gates'

// NOTE: Adding port 'qb' to entity

'gates'

// NOTE: Adding port 'd' to entity

'gates'

// NOTE: Adding port 'clk' to entity

'gates'

// NOTE: Adding port 'rst' to entity

'gates'

// NOTE: Adding VHDL generic 'delay _val' of type NATURAL to entity 'gates'

// NOTE: Adding equivalent VHDL signal assignment for gate instantiation 'firstnot'

<<<<<< VHDL translation of Verilog file 'example.v' being written to 'example.hdl' >>>>>>>

Output File : example.vhd

-- File Type: VHDL

-- Tool Version: verilog2vhdl v1.0 Mon Feb 6 16:59:45 EST 1995

-- Date Created: Mon Feb 13 15:11:35 1995

LIBRARY ieee;

USE ieee. std _logic _1164. all;

ENTITY gates IS

GENERIC (CONSTANT delay _val : natural := 3);

PORT (SIGNAL q : OUT std _logic;

SIGNAL qb : OUT std _logic;

SIGNAL d : IN std _logic;

SIGNAL clk : IN std _logic;

SIGNAL rst : IN std _logic);

END gates;

LIBRARY ASC;

ARCHITECTURE VeriArch OF gates IS

SIGNAL e : std _logic;

SIGNAL f : std _logic;

SIGNAL g : std _logic;

SIGNAL h : std _logic;

COMPONENT notif 0

GENERIC (CONSTANT bufdelay : time);

PORT (SIGNAL output : OUT std _logic;

SIGNAL input : IN std _logic;

SIGNAL enable : IN std _logic);

END COMPONENT;

USE ASC.buffers .all;

FOR ALL : notif0 USE ENTITY Verilog.notif0;

USE ASC.timing.all;

USE ASC.functions.all;

SIGNAL cf : std _logic;

SIGNAL a : std _logic;

SIGNAL b : std _logic;

SIGNAL c : std _logic;

BEGIN

qb <= ((cf nand clk) nand rst) AFTER parameter _delay(delay _val, ns);

qb <= ((cf or clk) or rst) AFTER delay(1, 2, 3, ns);

q<= ((((a xor b) xor e) xor f) xor g) AFTER 10ns;

q<= ((((a xor b) xor e) xor f) xor g) AFTER 1ns;

b <= (((d and e) and f) and g) AFTER 2ns;

e <= f AFTER 4ns;

g<= not h AFTER 4ns;

d<= not h AFTER 4ns;

dfirstnot : Verilog.buffers.notif0 PORT MAP (d, g, h);

END VeriArch;

VHDL Compilation

% vhdl _sim buffers.vhd

% vhdl _sim timing.vhd

% vhdl _sim numeric_std.vhd

% vhdl _sim functions.vhd

% vhdl _sim example.hdl <map logical library `Verilog' to the location where the compilation results of `buffers', `timing' , `numeric _std' and `functions' package(s) lie>

Since these packages are used extensively in Verilog2VHDL, it is suggested that the user pre-compile these packages. This will allow skipping the first few steps in the compilation for every run of Verilog2VHDL that uses these packages.

'-Package' switch usage Example

Input File: adders.v

// Base F-T 2-bit adder design with internal scan

module adders(a1, b1, a2, b2, s, test_clk, scan_en, scan_in0, scan_out, scan_in1);

input [ 1:0] a1, b1, a2, b2; input scan_in0, scan_in1; input test_clk, scan_en;

output s;

output [ 1:0] scan_out;

parameter wire_width = 2;

parameter scan_out_width = 1;

reg s;

reg [ scan_out_width:0] scan_out;

wire [wire_width:0] s1, s2;

half_adder add1 (.s(s1[ 0]), .co(add1co), .a(a1[ 0]), .b (b1[ 0])),

add3 (.s(s2[ 0]), .co(add3co), .a(a2[ 0]), .b(b2[ 0]));

aha add2 (.s(s1[ 1]), .co(s1[ 2]), .a(a1[ 1]), .b(b1[ 1]), .c(add1co)),

add4 (.s(s2[ 1]), .co(s2[ 2]), .a(a2[ 1]), .b(b2[ 1]), .c(add3co));

sc_mux cell1 (.D(s1[ 2]), .Q(cell1out), .clk(test_clk), .S_in(scan_in0),

.S_en (scan_en) ),

cell2 (.D(s1[ 1]), .Q(cell2out), .clk(test_clk), .S_in(cell1out),

.S_en (scan_en) ),

cell3 (.D(s1[ 0]), .Q(cell3out), .clk(test_clk), .S_in(cell2out),

.S_en (scan_en) ),

cell4 (.D(s2[ 2]), .Q(cell4out), .clk(test_clk), .S_in(scan_in1),

.S_en(scan_en) ),

cell5 (.D(s2[ 1]), .Q(cell5out), .clk(test_clk), .S_in(cell4out),

.S_en(scan_en) ),

cell6 (.D(s2[ 0]), .Q(cell6out), .clk(test_clk), .S_in(cell5out),

.S_en(scan_en) );

always @ (cell3out)

scan_out[ 0] = cell3out;

always @(cell6out)

scan _out[ 1] = cell6out;

// voter

always @(cell1out or cell2out or cell3out or cell4out or cell5out or cell6out)

begin

if ((cell1out == cell4out) & (cell2out == cell5out) & (cell3out == cell6out))

s = 1'b1;

else

s = 1'b0;

end

end module

Input files (2): files.v

// Verilog file for bit-wide adders

module aha(a,b,c,s,co);

input a,b,c;

output s,co;

parameter s_delay_min = 3,

s_delay_typ= 4,

s_delay_max = 5;

xor(a,b,c);

assign #(s_delay_min:s_delay_typ:s_delay_max) s = a;

assign #4 co = (a & b) ^(a & c) ^ (b & c);

endmodule

module half_adder (a,b,s,co);

input a,b;

output s,co;

parameter delay = 2;

assign #delay s = a ^ b;

and(a,b);

assign #delay co = a;

endmodule

// Verilog model of a muxed scan cell

module sc_mux(D, Q, clk, S_in, S_en);

input D, clk, S_in, S_en;

output Q;

reg Q;

wire dff_d;

mux2 mux (S_in, D, S_en, dff_d);

always @(posedge clk)

#1 Q = dff_d;

endmodule

module mux2 (a,b,en,y);

input a,b,en;

output y;

reg y;

always @(a or b or en)

begin

if (en == 1)

y = a;

else if (en == 0)

y = b;

else

y = 1'bz;

end

endmodule

Verilog2VHDL Invocation and Transcript

% v2v adders.v -p files.v

// Verilog2VHDL v1.0 Mon Feb 6 16:59:45 EST 1995

// Copyright(c) Alternative System Concepts Inc. 1992-1995, All
Rights Reserved.

// UNPUBLISHED, LICENSED SOFTWARE.

// CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE

// PROPERTY OF ALTERNATIVE SYSTEM CONCEPTS OR ITS LICENSORS.
//

// Running..

// NOTE: Adding VHDL entity 'adders' to output file

// NOTE: Adding VHDL architecture 'VeriArch' for entity 'adders'

// NOTE: Adding port 'a1' to entity 'adders'

// NOTE: Adding port 'b1' to entity 'adders'

// NOTE: Adding port 'a2' to entity 'adders'

// NOTE: Adding port 'b2' to entity 'adders'

// NOTE: Adding port 's' to entity 'adders'

// NOTE: Adding port 'test _clk' to entity 'adders'

// NOTE: Adding port 'scan_en' to entity 'adders'

// NOTE: Adding port 'scan _in0' to entity 'adders'

// NOTE: Adding port 'scan_out' to entity 'adders'

// NOTE: Adding port 'scan _in1' to entity 'adders'

// NOTE: Adding VHDL generic 'wire_width' of type NATURAL to entity 'adders'

// NOTE: Adding VHDL generic 'scan_out_width' of type NATURAL to entity 'adders'

// NOTE: Adding module instantiation 'add1' of module 'half_adder' in architecture 'VeriArch'

// NOTE: Adding module instantiation 'add3' of module 'half_adder' in architecture 'VeriArch'

// NOTE: Adding module instantiation 'add2' of module 'aha' in architecture 'VeriArch'

// NOTE: Adding module instantiation 'add4' of module 'aha' in architecture 'VeriArch'

// NOTE: Adding module instantiation 'cell1' of module 'sc_mux' in architecture 'VeriArch'

// NOTE: Adding module instantiation 'cell2' of module 'sc_mux' in architecture 'VeriArch'

// NOTE: Adding module instantiation 'cell3' of module 'sc_mux' in architecture 'VeriArch'

// NOTE: Adding module instantiation 'cell4' of module 'sc_mux' in architecture 'VeriArch'

// NOTE: Adding module instantiation 'cell5' of module 'sc_mux' in architecture 'VeriArch'

// NOTE: Adding module instantiation 'cell6' of module 'sc_mux' in architecture 'VeriArch'

// NOTE: Adding Process in architecture 'VeriArch' belonging to entity 'adders'

<<<<<< VHDL translation of Verilog file 'adders.v' being written to 'adders . hdl' >>>>>>>

<<<<<< VHDL package of Verilog file 'files.v' being written to 'files_pack. hdl' >>>>>>>>

Ouput file: adders.vhd

-- File Type: VHDL

-- Tool Version: verilog2vhdl v1.0 Mon Feb 6 16:59:45 EST 1995

-- Date Created: Mon Feb 13 15:15:31 1995

LIBRARY ieee;

USE ieee. std _logic _1164. all;

ENTITY adders IS

GENERIC (CONSTANT wire_width : natural := 2;

CONSTANT scan_out_width : natural := 1);

PORT (SIGNAL a1 : IN std_logic_vector(1 DOWNTO 0);

SIGNAL b1 : IN std_logic_vector(1 DOWNTO 0);

SIGNAL a2 : IN std_logic_vector(1 DOWNTO 0);

SIGNAL b2 : IN std_logic_vector(1 DOWNTO 0);

SIGNAL s : OUT std _logic;

SIGNAL test_clk : IN std_logic;

SIGNAL scan_en : IN std_logic;

SIGNAL scan_in0 : IN std_logic;

SIGNAL scan_out : OUT std_logic_vector(1 DOWNTO 0);

SIGNAL scan _in1 : IN std_logic);

END adders;

LIBRARY user_defined;

ARCHITECTURE VeriArch OF adders IS

FOR ALL : half_adder USE ENTITY user_defined.half_adder;

FOR ALL : sc_mux USE ENTITY user_defined.sc_mux;

SIGNAL s1 : std _logic _vector(wire_width DOWNTO 0);

SIGNAL cell3out : std _logic;

SIGNAL cell2out : std _logic;

SIGNAL cell1out : std _logic;

SIGNAL add1co : std _logic;

FOR ALL : aha USE ENTITY user_defined.aha;

USE user_defined.files_pack.all;

SIGNAL s2 : std_logic_vector(wire_width DOWNTO 0);

SIGNAL cell6out : std_logic;

SIGNAL cell5out : std_logic;

SIGNAL cell4out : std_logic;

SIGNAL add3co : std_logic;

BEGIN

add1 : user_defined.files_pack.half_adder

PORT MAP

(s => s1(0),

co => add1co,

a => a1(0),

b => b1(0)) ;

add3 : user_defined.files_pack.half_adder

PORT MAP

(s => s2(0),

co => add3co,

a => a2(0),

b => b2(0)) ;

add2 : user_defined.files_pack.aha

PORT MAP

(s => s1(1),

co => s1(2),

a => a1(1),

b => b1(1),

c => add1co) ;

add4 : user_defined.files _pack.aha

PORT MAP

(s => s2(1),

co => s2(2),

a => a2(1),

b => b2(1),

c => add3co) ;

cell1 : user_defined.files_pack.sc_mux

PORT MAP

(D => s1(2),

Q => cell1out,

clk => test _clk,

S_in => scan _in0,

S_en => scan _en) ;

cell2 : user_defined.files_pack.sc_mux

PORT MAP

(D => s1(1),

Q => cell2out,

clk => test _clk,

S_in => cell1out,

S_en => scan_en);

cell3 : user_defined.files_pack.sc_mux

PORT MAP

(D => s1(0),

Q => cell3out,

clk => test _clk,

S_in => cell2out,

S_en => scan_en) ;

cell4 : user_defined.files_pack.sc_mux

PORT MAP

(D => s2(2),

Q => cell4out,

clk => test _clk,

S_in => scan _in1,

S_en => scan_en) ;

cell5 : user_defined.files_pack.sc_mux

PORT MAP

(D => s2(1),

Q => cell5out,

clk => test _clk,

S_in => cell4out,

S_en => scan_en) ;

cell6 : user_defined.files_pack.sc_mux

PORT MAP

(D => s2(0),

Q => cell6out,

clk => test _clk,

S_in => cell5out,

S_en => scan_en) ;

PROCESS

BEGIN

WAIT ON cell3out;

scan _out(0) <= cell3out;

END PROCESS;

PROCESS

BEGIN

WAIT ON cell6out;

scan _out(1) <= cell6out;

END PROCESS;

PROCESS

BEGIN

WAIT ON cell1out, cell2out, cell3out, cell4out, cell5out, cell6out;

IF ((cell1out = cell4out) and (cell2out = cell5out) and (cell3out = cell6out)) THEN

s <= '1';

ELSE

s <= '0';

END IF;

END PROCESS;

END VeriArch;

Output File 2: files_pack.vhd

-- File Type: VHDL

-- Tool Version: verilog2vhdl v1.0 Mon Feb 6 16:59:45 EST 1995

-- Date Created: Mon Feb 13 15:15:31 1995

LIBRARY ieee;

USE ieee. std _logic _1164. all;

ENTITY mux2 IS

PORT (SIGNAL a : IN std _logic;

SIGNAL b : IN std _logic;

SIGNAL en : IN std _logic;

SIGNAL y : OUT std _logic);

END mux2;

LIBRARY ieee;

USE ieee. std _logic _1164. all;

ENTITY aha IS

GENERIC (CONSTANT s_delay_min : natural := 3;

CONSTANT s_delay_typ : natural := 4;

CONSTANT s_delay_max : natural := 5);

PORT (SIGNAL a : IN std _logic;

SIGNAL b : IN std _logic;

SIGNAL c : IN std _logic;

SIGNAL s : OUT std _logic;

SIGNAL co : OUT std _logic);

END aha;

LIBRARY ASC;

ARCHITECTURE VeriArch OF aha IS

USE ASC.timing.all;

BEGIN

a <= (b xor c);

s <= a AFTER delay(s _delay _min, s_delay_typ, s_delay_max, NS);

co <= (a and b) xor (a and c) xor (b and c) AFTER 4NS;

END VeriArch;

LIBRARY ieee;

USE ieee. std _logic _1164. all;

ENTITY half_adder IS

GENERIC (CONSTANT delay : natural := 2);

PORT (SIGNAL a : IN std _logic;

SIGNAL b : IN std _logic;

SIGNAL s : OUT std _logic;

SIGNAL co : OUT std _logic);

END half_adder;

LIBRARY ASC;

ARCHITECTURE VeriArch OF half_adder IS

USE ASC.timing.all;

BEGIN

s <= a xor b AFTER parameter _delay(delay, NS);

a <= b;

co <= a AFTER parameter _delay(delay, NS);

END VeriArch;

LIBRARY ieee;

USE ieee. std _logic _1164. all;

ENTITY sc_mux IS

PORT (SIGNAL D : IN std _logic;

SIGNAL Q : OUT std _logic;

SIGNAL clk : IN std _logic;

SIGNAL S_in : IN std _logic;

SIGNAL S_en : IN std _logic);

END sc_mux;

ARCHITECTURE VeriArch OF sc_mux IS

SIGNAL dff_d : std _logic;

COMPONENT mux2

PORT (SIGNAL a : IN std _logic;

SIGNAL b : IN std _logic;

SIGNAL en : IN std _logic;

SIGNAL y : OUT std _logic);

END COMPONENT;

FOR ALL : mux2 USE ENTITY work.mux2;

BEGIN

PROCESS

BEGIN

WAIT UNTIL posedge(clk);

WAIT FOR 1NS;

Q <= dff_d;

END PROCESS;

mux : mux2 PORT MAP (S_in, D, S_en, dff_d) ;

END VeriArch;

ARCHITECTURE VeriArch OF mux2 IS

BEGIN

PROCESS

BEGIN

WAIT ON a, b, en;

IF en = '1' THEN

y <= a;

ELSE

IF en = '0' THEN

y <= b;

ELSE

y <= 'Z';

END IF;

END PROCESS;

END VeriArch;

LIBRARY ieee;

USE ieee. std _logic _1164. all;

PACKAGE files_pack IS

COMPONENT mux2

PORT (SIGNAL a : IN std _logic;

SIGNAL b : IN std _logic;

SIGNAL en : IN std _logic;

SIGNAL y : OUT std _logic);

END COMPONENT;

COMPONENT aha

GENERIC (CONSTANT s_delay_min : natural := 3;

CONSTANT s_delay_typ : natural := 4;

CONSTANT s_delay_max : natural := 5);

PORT (SIGNAL a : IN std _logic;

SIGNAL b : IN std _logic;

SIGNAL c : IN std _logic;

SIGNAL s : OUT std _logic;

SIGNAL co : OUT std _logic);

END COMPONENT;

COMPONENT half_adder

GENERIC (CONSTANT delay : natural := 2);

PORT (SIGNAL a : IN std _logic;

SIGNAL b : IN std _logic;

SIGNAL s : OUT std _logic;

SIGNAL co : OUT std _logic);

END COMPONENT;

COMPONENT sc_mux

PORT (SIGNAL D : IN std _logic;

SIGNAL Q : OUT std _logic;

SIGNAL clk : IN std _logic;

SIGNAL S_in : IN std _logic;

SIGNAL S_en : IN std _logic);

END COMPONENT;

COMPONENT mux2

PORT (SIGNAL a : IN std _logic;

SIGNAL b : IN std _logic;

SIGNAL en : IN std _logic;

SIGNAL y : OUT std _logic);

END COMPONENT;

END;

VHDL Compilation

Verilog2VHDL writes out VHDL packages for the Verilog files read in by the `-Package' switch. The name of the VHDL package is `<pkg_filename_without_extension>_pack' and the VHDL filename is <pkg_filename_without_extension>_pack.hdl. For e.g, if a Verilog file of the name files.v is read into the Verilog2VHDL database, the subsequent VHDL package `files_pack' would be placed in file files_pack.hdl.

% vhdl _sim timing.vhd

% vhdl _sim files _pack.hdl

% vhdl _sim adders.hdl <map Logical library `user _defined' to the VHDL compilation results of `files' package>

In the case when there is more than one logical library in the final VHDL, each logical library needs to be mapped to the physical location of the VHDL compilation results.