•Press the Project Simulation Properties button or choose the Project > Project Simulation Properties menu to open the dialog.

•Select Template Configurations to edit the default settings that are used by new projects. These are stored in the INI file each time the program is closed. The Restore Default Templates button (at the bottom of the dialog) is used to reset the INI file to the factory default settings for this dialog.

•Select Diagram Configuration to edit the options for how diagrams are simulated (simulated signals in a Diagram window). These are stored in the INI file.

•Select Project Configurations to edit the project settings for the current project. These settings are stored in the project HPJ file when you save the project.

•Press the Add button to open the Add New Configuration dialog and you specify a name and the default configuration to copy settings from.

•Rename button lets you change the name of the current configuration.

•Delete removes the current configuration.

•Use the Configurations drop-down to choose which configuration is currently active (e.g. which settings will be used for compiling and running simulations).

•Clear Log File Before Compile clears the simulation log just prior to a new compilation being performed. This log maintains compilation notes, as well as some simulation notes. Note that in this dialog you can also change the name of this log (see Logfile below).

•Break at Time Zero is the equivalent of setting a breakpoint at time zero. This starts the simulator and allows you to enter commands into the console window that will be executed at the start of the simulation.

•Generate Test Bench on Build Project automatically updates the test bench for changes to timing diagrams. Turn this off if you want to temporarily change some of the generated source code manually or to avoid updating the test bench on diagram changes.

•When the Auto Parse Project on Load box is checked, user source files are automatically parsed and built when the project is loaded. The top-level component is the first module that is not included by another module for Verilog; it is the first entity/architecture pair parsed for VHDL. This is mainly used by Actel Libero customers with WaveFormer Lite.

•Compile Source Files of Type section specifies which kind of files to compile. This is especially important for V2V translation projects, and projects with mixed language code. Consider using this along with the above Configurations setting, by having a VHDL configuration and a Verilog configuration for doing different simulations.

•Log File specifies the name of the log file that receives all the simulation results and information. By default BugHunter uses simulation.log.

•Auto-Grab Top Level Signals causes signals in the top-level component to be automatically added as Watch signals in the stimulus and results diagram whenever the project is rebuilt

•Dump Watched Signals generates a dump file for any watched signals in the diagram. The generated file will named diagramName.VCD.

•Capture and Show Waveforms of Watched Signals enables the display of waveform results from a simulation run.

•When Disable Periodic Waveform Update (faster sim time) is unchecked, all simulation waveforms are flushed across to the Stimulus and Results Diagram window every 5 seconds. Checking this causes waveforms to only be updated when sufficient data has built up or when the simulator is paused or stopped.

•When Make Constants and Parameters Watchable is unchecked then these objects will not be watched when you ask to watch all contents of a component.

•When Make Arrays Watchable Up To: xxx Elements (0 for all) is unchecked, array elements will not be watched when you ask to watch all the contents of a component. Even if it is checked, you can limit the number of array elements that get dumped for each array (in order to prevent creating too many watched signals from being generated when watching a large memory array, for example). If you really want to dump all array elements, no matter how large the array, set the Elements limit to 0.

•Filter Constants and Parameters will hide these objects in the project tree to make the tree size more manageable.

•Filter Empty Processes will hide processes in the project tree that do not contain signals or variables.

•The Override Subproject Properties during Simulation works only with TestBencher and forces the compiler to use only the top-level project settings to build and run the subprojects.

•Simulator Type specifies the simulator.

•The Simulator Settings button opens the Simulator / Compiler Settings dialog where you can edit the simulator paths.

•Include Directories specifies the directories where BugHunter searches for included files. The following is a Windows example (Unix users should use the / slashes):

C:\design\project;c:\design\library

•The Library Directories box lists the path and directories where the program searches for library files. BugHunter will try to match any undefined components with the names of the files that have one of the file extensions listed in the Lib Extensions edit box. The simulator does not look inside a file unless the undefined component name exactly matches a file name. The simulator does not look at any files unless there are file extensions listed in the Lib Extensions edit box. Note that this works even with compiled code simulators that don't normally support the -y option. The following is a Windows example (Unix users should use the / slashes):

C:\design\project;c:\design\library

•The Lib Extensions box specifies the file name extension used when searching for library files in the library directory. Each library extension should begin with the period character followed by the extension name. Use a semicolon to separate multiple file extensions.

.v;.vo

•The Delay Settings radio buttons determines which delay value is used in min:typ:max expressions. These settings are output as either the +maxdelays, +mindelays, or +typdelays command line simulator option.

•The Snapshot box accepts a text string that will become the name of the simulation that is built (overriding the normal name of the simulation build).

•Compile, Elaborator, and Simulator option edit boxes allow you to write additional command line options that will be passed to each tool when it is run. If you want to compile an existing design that is normally compiled using a command line simulator, you can easily compile this kind of design by setting the same options here (see 2.12 Compiling Command-Line Based Designs for details). Note that not all simulators support all three phases of command line options.

•By default, simulation options are expected to be specified using Simx-syntax (discussed in Chapter 5). BugHunter will automatically translate these options to the appropriate form for the target simulator. If you want to pass options from another simulator, you can use the "simulation translation mode" options to change the mode BugHunter expects options to be in (see Section 12.3 SimSwapper Translation Modes).

•The Drive Events using PLI checkbox changes the way stimulus from the StimulusAndResults diagram is sent to the simulator. By default, stimulus waveforms cause Verilog stimulus code to be compiled into the simulation (see Section 3.2: Drawing Waveforms for Stimulus Generation). But when this option is checked, stimulus is directly injected into the simulation at runtime via a PLI application  that reads from the  btim timing diagram file. This allows you to change the stimulus by editing the btim file without requiring a recompile of your simulation. The disadvantage of this approach is that you cannot single step through the stimulus, since it's injected via PLI.

•The Extra File Extensions to Compile adds more types of files that will be treated as  Verilog files.

•When the Generate Command File button is pushed, the text contained in the Simulator Options edit box along with the list of Verilog files specified in the Project window are written to a Command File. This file can then be used with the Command Line version of your simulator to run a simulation without the BugHunter GUI.

•The Override Subproject Properties during Simulation works only with TestBencher and forces the compiler to use only the top-level project settings to build and run the subprojects.

•Simulator Type determines the simulator.

•The Simulator Settings button opens the Simulator / Compiler Settings dialog where you can edit the simulator paths.

•The Destination Library controls the logical library that sources files will be compiled into when a build is performed.

•The VHDL 93 checkbox specifies that the project dialect for the generated files is VHDL 93.

•The Compile, Elaborator, and Simulator options edit box allow you to write additional command line options that will be passed to the tool when it is run. Most simulators do not support all three phases of command line options.

•The Extra File Extensions to Compile adds more types of files that will be treated as VHDL files.

•The Override Subproject Properties during Simulation works only with TestBencher and forces the compiler to use only the top-level project settings to build and run the subprojects.

•Compiler Type specifies the C++ compiler.

•The Compiler Settings button opens the Simulator / Compiler Settings dialog where you can review and edit the compiler paths.

•The Run Target Executable sets the name for the executable program that will be built/run from the C++ source code in the project.

•The Include Directories specifies the include directories that will be searched for header files when files are included into a source file.

•The Library Directories specifies the directories to search for library files during the build process.

•The Compile, Linker, and Run Time options edit box allow you to write additional command line options that will be passed to the tool when it is run.