What if I have a question that isn't answered on this page?

If you run into a problem that does not have a solution on this page please send the following information, if available, to [email protected]:

•A detailed description of the problem, including under what circumstances the problem occurred, what version of the product you are using and on what platform you are using it.

•The log file: vhdl2v.log or v2v.log.

•The error message: cut and save the screen mesage to a file and attach it to your e-mail.

•The command line

•The input and output files

We will begin investigating the problem immediately, and respond to you as quickly as possible.

Can v2v handle the compiler directive 'include?

Yes. The 'include directive is handled by Vpp, the "Verilog Pre-Processor." It is in the "bin" subdirectory after you install the Translator. The translator will automatically run vpp on your source files.

Vpp deals with some of the compiler directives such as 'include. The output file of Vpp is still a Verilog file, which may be translated automatically by the verilog2vhdl translator.

I received a warning message during translation that I used a reserved word in my code, or the identifier is not a legal VHDL identifier. What does it mean?

v2v has a list of reserved words, such as "input" "output" "mod", etc, that can not be used as identifiers. Also, some legal identifiers in Verilog are not legal in VHDL, such as an identifier like "name_".

The Translator treats this case as a warning. It adds a slash "/" to both ends of the identifier, such as "/name_/", and gives out a warning message to remind the user.

Please look at verilog2vhdl and VHDL2Verilog manuals as a part of this documentation to see a complete list of reserved words.

Can v2v translate modules with multiple levels of instantiation? Yes!

Suppose you have a module A (in file "file1 .v") that instatiates module B (in file "package1 .v") and C ("package2.v"). In this case, you would use the following command line:

v2v file1.v file1.vhd -p package1.v package2.v

Now consider a situation in which module B also instantiates module D (in file "package3.v"). In this case you would use the following command line:

v2v file1.v file1.vhd -p package3.v package1.v package2.v

Please note, in the second case, the sequence of the package files matters. You have to put the lowest level module first, then the higher level modules.

In some situations you might not want to check the existence of some lower level modules while you are translating the top level module. Use the -nc option to achieve this. You can see all the options with the command v2v -h or by reading the users' manual.

How does v2v perform error handling?

v2v handles errors in the following ways:

1.If a syntax error in encountered in the input file, the tool exits immediately after printing out the error message.

2.If an unsupported construct is encountered in the input, a warning message is issued, and  v2vcontinues processing.

3.If the unsupported construct is of the type `event', v2v exits after issuing an appropriate error message.

What Verilog constructs are not supported?

•UDPs

•Assign and deassign procedural assignments

•Force and release procedural assignments

•Parallel blocks (such as fork-join blocks)

•Task disable

•Specify blocks

•There are some system functions not supported, such as the ones for timing check.

The supported and unsupported constructs are listed in detail in the user's manual, as well as some workarounds to common problems.

How do I verify the translation result?

v2v keeps functional equivalence of the Verilog design and the translated VHDL design. It is intended to be used to enhance productivity by saving much of the labor of manual translation. Some language constructs may not be translated automatically due to language disparities.

You can use any simulation tool to verify the functionality of a translated file. Equivalence checkers can also be used to detect equivalence errors.

All the library files needed for simulation of the generated code are included in the package. When you compile these library files, please follow the instructions about the sequence in the v2v Manual  in the section entitled "post-translation" (DLNFIX).

I use the Synopsys synthesis and simulation environment. Is there anything I need to take into consideration?

Package files compliant with the SYNOPSYS simulation and synthesis environment are located in the $SYNCAD_HOME/libsyn directory. Filenames are almost the same as described below; the only difference being that files in the $SYNCAD_HOME/libsyn have a '_syn' extension. Therefore, the file buffers.vhd in the $SYNCAD_HOME/lib is equivalent to file buffers_syn.vhd in the libsyn directory.

Why do I receive compilation errors when I compile translated VHDL files?

In some cases, the automatic translation cannot complete due to unsupported constructs. Hand modification is required to make the translation compilable.

Sometimes you receive compilation errors because some simulation/synthesis tools have problems with supporting IEEE1 076-1993. Use ***_87 instead. The readmem.vhd, textio_header.vhd, and standard.vhd are compliant with VHDL-93. If you must use them, please refer to the simulation/synthesis tool's manual and modify the files to make them compatible to the tool.