3.3 Simulated Buses

Simulated buses are similar to Group buses in that they have member signals. However, unlike a group bus, the simulated bus is exported to VHDL and Verilog along with its member signals. Simulated Buses were created for the test bench products so that both the bus and the individual signals could be passed into models as needed. A simulated bus is automatically defined as a concatenation of the member signals.

Create a Simulated Bus:

•Click the Add Bus button to open the Add Bus dialog.

•Select the Simulated Bus radio button, and type in a Name, an MSB, and an LSB into the corresponding boxes and close the dialog to place the new bus and its member signals in the timing diagram.

For more information on simulated signals see Chapter 4: Simulated Signals - Boolean Equations. For a quick look at the definition of the simulated bus, double click on the bus name to open the Signals Properties dialog and view the Boolean Equation that defines the bus. For example a simulated bus looks like {BUS2_3,BUS2_2,BUS2_1,BUS2_0}.