Chapter 4: Simulated Signals and VHDL/Verilog Export |
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Chapter 4: Simulated Signals and VHDL/Verilog Export |
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Chapter 4: Simulated Signals and VHDL/Verilog Export |
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Chapter 4: Simulated Signals and VHDL/Verilog Export |
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SynaptiCAD's simulation-enabled products (like WaveFormer Pro and DataSheetPro) contain a built-in Interactive HDL Simulator that is capable of simulating Boolean and registered logic equations. The simulator is interactive, because changes to the input waveforms cause the simulated waveforms to redraw. This feature greatly reduces the amount of time needed to draw a timing diagram, especially one that models gate level circuits.
Products like WaveFormer Pro that have export enabled, and also generate VHDL and Verilog stimulus models from the timing diagram. All of the signal types are language independent so the same timing diagram can be used to generate models for both languages.