Timing diagrams can generate SDC files. In addition, multiple SDC files can be linked together to generate one file. Synopsys Design Constraint (SDC) files are used to provide additional design requirements for timing performance to design synthesis tools that accept Verilog and VHDL RTL code as input. In other words, the input RTL code describes the desired logical function of the design and the SDC file describes the timing constraints the design must operate under. SynaptiCAD's timing diagram editors simplify the creation of SDC files in several ways: 1) SDC commands can be generated from timing parameters in timing diagrams, 2) SDC commands can be edited.