Step 3: Generate the Reactive Test Bench

For the Reactive Test Bench Option, the test bench generation step is just a simple export to a particular file format.

To export a timing diagram:

•Select the Import/Export > Export Timing Diagrams As menu option to open a special version of the Save As dialog which remembers the file type of the last file exported.

•Select a VHDL or Verilog export format from the Save as type box, enter a file name, and click Save button to generate the file.

vhdl_ver_saveas

The plain VHDL or Verilog formats generates a stimulus module that can be included into a user-written top level test bench.

The Top Level Test Bench types instantiates the model in the Project window and the stimulus model within a top-level model. This top-level module can then be simulated without any additional setup.

The VCD format generates a stimulus file that can be read by other EDA tools and test equipment (not a test bench model).

•The generated file will open as a tab in the Report window so you can quickly see how changes in the diagram affect the generated code.

report_export

VHDL Library and Use Clause statement support:

If Libraries or Use Clauses need to be added to the generated model, then specify them in the VHDL Libraries and Use Clauses to Include dialog.

•Choose the Options > VHDL Libraries and Use Clauses menu to open the dialog. Changes made in this dialog will be applied to all diagrams that are exported to VHDL.

•From the View control select either Use Clauses or VHDL Libraries and enter the information on to a blank row.

useClauses&Libraries

•If the ‘USE’ is omitted from a use clause, or the ‘LIBRARY’ from a library statement, WaveFormer will automatically add ‘USE’ or ‘LIBRARY’ before the clause in the source file for the diagram. If necessary, WaveFormer will also automatically add semicolons to the end of library includes and use clauses