9.4 Libraries and Use Clauses dialog (VHDL)

The VHDL Libraries and Use Clauses to Include dialog allows you to control the libraries and use clauses used by the VHDL diagrams in your project and by the top-level template file of the project. Changes made in this dialog will be applied to the current project, and stored in the .hpj file. If no project is open then the current settings will be applied to any new projects that are created, and saved in the TestBencher configuration.

VHDL Library and Use Clause dialog controls for VHDL support:

•Choose the Options > VHDL Libraries and Use Clauses menu to open the dialog. Changes made in this dialog will be applied to all diagrams that are exported to VHDL.

•From the View control select either Use Clauses or VHDL Libraries and enter the information onto a blank row.

useClauses&Libraries

•If the ‘USE’ is omitted from a use clause, or the ‘LIBRARY’ from a library statement, WaveFormer will automatically add ‘USE’ or ‘LIBRARY’ before the clause in the source file for the diagram. If necessary, WaveFormer will also automatically add semicolons to the end of library includes and use clauses

•All three of the following use clauses will work:

use myLib1.all;

myLib2.all;

myLib3.all

•All three of the following VHDL Library statements will work:

library myLib1;

myLib2;

myLib3

Exporting a single diagram to VHDL

Whenever VHDL code is generated for a diagram, TestBencher checks to see if the diagram is included in the current project. If it is, then the settings for that project are used. If the diagram is not included in the current project, then the diagram will be exported using the default settings for all diagrams.