Operator Name

Equations

States

Autogen

Syncad

Example

Definition

Parentheses

yes

yes

yes

( )

(a + b)

Groups expressions

Bit Concatenation

yes

yes

yes

{ }

{ a, b, ..., z }

Concatenates operands sequentially

Bit Replication

yes

yes

yes

{{ }}

{ n {a} }

Concatenates a n times

Selection

yes

yes

yes

[ ]

a[i]

Selects a piece of the operand

Hierarchy

yes

yes

yes

.

a.b

Hierarchically accesses scope

List Slice

no

yes

no

..

a[0..5]

See e Language Reference manual

List Concatenation

no

yes

no

{ ; }

{a;b;c}

See e Language Reference manual

Operator Name

Equations

States

Autogen

Syncad

Example

Definition

Bit Slice

yes

yes

yes

: or

to or downto

a[3:0]

Used with Selection operator to select a range of bits

Operator Name

Equations

States

Autogen

Syncad

Example

Definition

Class

no

yes

no

@

@class1

Specifies that the name following @ is an instance of a user defined class

State Variable

no

yes

no

$$

$$addr

Specifies that the name following $$ is a State Variable

Macro Definition

no

yes

no

`

`base_address

Refers to a defined macro

Operator Name

Equations

States

Autogen

Syncad

Example

Definition

Logical Negation

yes

yes

yes

!

(any)

!a

Converts a nonzero operand into 0 and a zero operand into 1

Bit-wise Negation

yes

yes

yes

~

(any)

~a

Performs bit-wise negation of operand

Absolute Value

yes

yes

yes

abs( )

abs( a )

Negates operand if it is negative.  Otherwise, operand is not changed.

Exponentiation

yes

yes

yes

**

a ** 2

See VHDL Language Reference Manual

Identity

yes

yes

yes

+

+a

Leaves operand unchanged

Negation

yes

yes

yes

-

-a

Negates operand

Operator Name

Equations

States

Autogen

Syncad

Example

Definition

Multiply

yes

yes

yes

*

a * b

Multiplies left and right operands

Divide

yes

yes

yes

/

a / b

Divides left and right operands

Modulo

yes

yes

yes

mod

a mod b

See VHDL Language Reference Manual

Remainder

yes

yes

yes

%

(any)

a % b

Performs division operation and returns the remainder

Operator Name

Equations

States

Autogen

Syncad

Example

Definition

Addition

yes

yes

yes

+

a + b

Adds left and right operands

Subtraction

yes

yes

yes

-

a - b

Subtracts right operand from left operand

Operator Name

Equations

States

Autogen

Syncad

Example

Definition

Shift Left Logical

yes

yes

yes

<<

(any)

a << 5

Performs left shift of left operand by the number of bit positions specified by right operand

Shift Right Logical

yes

yes

yes

>>

(any)

a >> 5

Performs right shift of left operand by the number of bit positions specified by right operand

Shift Left Arithmetic

yes

yes

yes

sla

a sla 5

See VHDL Language Reference Manual

Shift Right Arithmetic

yes

yes

yes

sra

a sra 5

See VHDL Language Reference Manual

Rotate Left

yes

yes

yes

rol

a rol 5

See VHDL Language Reference Manual

Rotate Right

yes

yes

yes

ror

a ror 5

See VHDL Language Reference Manual

Operator Name

Equations

States

Autogen

Syncad

Example

Definition

Less Than

yes

yes

yes

<

a < b

Returns TRUE if the first expression is smaller than the second expression

Less Than or Equal

yes

yes

yes

<=

a <= b

Returns TRUE if the second expression is not smaller than the first expression

Greater Than

yes

yes

yes

>

a > b

Returns TRUE if the second expression is greater than the second expression

Greater Than or Equal

yes

yes

yes

>=

a >= b

Returns TRUE if the first expression is not smaller than the second expression

Operator Name

Equations

States

Autogen

Syncad

Example

Definition

Positive Subtype Identification

no

yes

no

is a

a is a b

See e Language Reference manual

Negative Subtype Identification

no

yes

no

is not a

a is not a b

See e Language Reference manual

Operator Name

Equations

States

Autogen

Syncad

Example

Definition

Equality

yes

yes

yes

==

a == b

Results in 1 if operands are same, 0 otherwise

Inequality

yes

yes

yes

any

a != b

Results in 1 if operands are different, 0 otherwise

Case Equality

yes

yes

yes

any

a === b

Results in 1 if operands are same, 0 otherwise

Case Inequality

yes

yes

yes

any

a !== b

Results in 1 if operands are different, 0 otherwise

Wild Equality

no

yes

yes

=?=

a =?= b

Results in 1 if operands are same, 0 otherwise (x and z are wildcards)

Wild Inequality

no

yes

yes

!?=

a !?= b

Results in 1 if operands are different, 0 otherwise (x and z are wildcards)

Operator Name

Equations

States

Autogen

Syncad

Example

Definition

In Range List

no

yes

no

in

a in b

See e Language Reference manual

Positive String Matching

no

yes

no

~

a ~ b

See e Language Reference manual

Negative String Matching

no

yes

no

!~

a !~ b

See e Language Reference manual

Operator Name

Equations

States

Autogen

Syncad

Example

Definition

Bit-wise AND

yes

yes

yes

&

a & b

Performs bit-wise AND of two operands

Reduction AND

yes

yes

yes

&

&a

Performs bit-wise AND of one operand and results in a single bit

Reduction NAND

yes

yes

yes

~&

~&a

Performs bit-wise NAND of one operand and results in a single bit

Operator Name

Equations

States

Autogen

Syncad

Example

Definition

Bit-wise XOR

yes

yes

yes

^

a ^ b

Performs bit-wise XOR of two operands

Reduction XOR

yes

yes

yes

^

^a

Performs bit-wise XOR of one operand and results in a single bit

Bit-wise XNOR

yes

yes

yes

^~ or ~^

a ^~ b

Performs bit-wise XNOR of two operands

Reduction XNOR

yes

yes

yes

^~ or ~^

^~a

Performs bit-wise XNOR of one operand and results in a single bit

Operator Name

Equations

States

Autogen

Syncad

Example

Definition

Bit-wise OR

yes

yes

yes

|

a | b

Performs bit-wise OR of two operands

Reduction OR

yes

yes

yes

|

|a

Performs bit-wise OR of one operand and results in a single bit

Bit-wise NOR

yes

yes

yes

nor

(any)

a |~ b

Performs bit-wise NOR of two operands

Reduction NOR

yes

yes

yes

~|

~|a

Performs bit-wise NOR of one operand and results in a single bit

Bit-wise NAND

yes

yes

yes

nand

a nand b

Performs bit-wise NAND of two operands

VHDL Bit-wise XNOR

yes

yes

yes

xnor

a xnor b

Performs bit-wise XNOR of two operands

VHDL Bit-wise XOR

yes

yes

yes

xor

a xor b

Performs bit-wise XOR of two operands

VHDL Bit-wise OR

yes

yes

yes

or

a or b

Performs bit-wise OR of two operands

VHDL Bit-wise AND

yes

yes

yes

and

a and b

Performs bit-wise AND of two operands

Operator Name

Equations

States

Autogen

Syncad

Example

Definition

Logical AND

yes

yes

yes

&&

a && b

If both operands are non-zero then result is 1, otherwise result is 0

Operator Name

Equations

States

Autogen

Syncad

Example

Definition

Logical OR

yes

yes

yes

||

a || b

If either operand is non-zero then result is 1, otherwise result is 0

Operator Name

Equations

States

Autogen

Syncad

Example

Definition

Boolean Implication

yes

yes

yes

=>

a => b

If both operands are true or first operand is false, then result is 1, otherwise result is 0.

Boolean Event Check

no

yes

no

now @

now @sys.a

See e Language Reference manual

Operator Name

Equations

States

Autogen

Syncad

Example

Definition

Ternary

yes

yes

yes

? :

(any)

(condition) ?a:b

If condition is TRUE then result is a, otherwise result is b.

Operator Name

Equations

States

Autogen

Syncad

Example

Definition

Delay

yes

no

no

delay

SIG0 delay 5

Delays left operand by time specified by right operand

Operator Name

Syncad

Verilog

VHDL

e

OpenVera

TestBuilder

Parentheses

( )

( )

( )

( )

( )

( )

Bit Concatenation

{ }

{ }

&

%{ }

{ }

n/a

Bit Replication

{{ }}

{{ }}

n/a

n/a

n/a

n/a

Selection

[ ]

[ ]

[ ]

[ ]

[ ]

( )

Hierarchy

.

.

n/a

. or ~/ /

.

.

List Slice

..

n/a

n/a

..

n/a

n/a

List Concatenation

{ ; }

n/a

n/a

{ ; }

n/a

n/a

Operator Name

Syncad

Verilog

VHDL

e

OpenVera

TestBuilder

Bit Slice

: or

to or downto

:

to or downto

:

:

, (comma)

Operator Name

Syncad

Verilog

VHDL

e

OpenVera

TestBuilder

Class

@

n/a

n/a

n/a

n/a

n/a

State Variable

$$

n/a

n/a

n/a

n/a

n/a

Macro Definition

`

`

n/a

`

Operator Name

Syncad

Verilog

VHDL

e

OpenVera

TestBuilder

Logical Negation

!

(any)

!

not

!

!

!

Bit-wise Negation

~

(any)

~

not

~

~

~

Absolute Value

abs( )

n/a

abs( )

n/a

n/a

abs()

Exponentiation

**

n/a

**

n/a

n/a

n/a

Identity

+

+

+

+

+

+

Negation

-

-

-

-

-

-

Operator Name

Syncad

Verilog

VHDL

e

OpenVera

TestBuilder

Multiply

*

*

*

*

*

*

Divide

/

/

/

/

/

/

Modulo

mod

n/a

mod

n/a

n/a

n/a

Remainder

%

(any)

%

rem

%

%

%

Operator Name

Syncad

Verilog

VHDL

e

OpenVera

TestBuilder

Addition

+

+

+

+

+

+

Subtraction

-

-

-

-

-

-

Operator Name

Syncad

Verilog

VHDL

e

OpenVera

TestBuilder

Shift Left Logical

<<

(any)

<<

sll

<<

<<

<<

Shift Right Logical

>>

(any)

>>

srl

>>

>>

>>

Shift Left Arithmetic

sla

n/a

sla

n/a

n/a

n/a

Shift Right Arithmetic

sra

n/a

sra

n/a

n/a

n/a

Rotate Left

rol

n/a

rol

n/a

n/a

n/a

Rotate Right

ror

n/a

ror

n/a

n/a

n/a

Operator Name

Syncad

Verilog

VHDL

e

OpenVera

TestBuilder

Less Than

<

<

<

<

<

<

Less Than or Equal

<=

<=

<=

<=

<=

<=

Greater Than

>

>

>

>

>

>

Greater Than or Equal

>=

>=

>=

>=

>=

>=

Operator Name

Syncad

Verilog

VHDL

e

OpenVera

TestBuilder

Positive Subtype Identification

is a

n/a

n/a

is a

n/a

n/a

Negative Subtype Identification

is not a

n/a

n/a

is not a

n/a

n/a

Operator Name

Syncad

Verilog

VHDL

e

OpenVera

TestBuilder

Equality

==

==

=

==

==

==

Inequality

any

!=

/=

!=

!=

!=

Case Equality

any

===

n/a

===

===

n/a

Case Inequality

any

!==

n/a

!==

!==

n/a

Wild Equality

=?=

n/a

n/a

n/a

=?=

n/a

Wild Inequality

!?=

n/a

n/a

n/a

!?=

n/a

Operator Name

Syncad

Verilog

VHDL

e

OpenVera

TestBuilder

In Range List

in

n/a

n/a

in

n/a

n/a

Positive String Matching

~

n/a

n/a

~

n/a

n/a

Negative String Matching

!~

n/a

n/a

!~

n/a

n/a

Operator Name

Syncad

Verilog

VHDL

e

OpenVera

TestBuilder

Bit-wise AND

&

&

n/a

&

&

&

Reduction AND

&

&

n/a

n/a

&

.reductionAnd()

Reduction NAND

~&

~&

n/a

n/a

~&

.reductionNand()

Operator Name

Syncad

Verilog

VHDL

e

OpenVera

TestBuilder

Bit-wise XOR

^

^

n/a

^

^

^

Reduction XOR

^

^

n/a

n/a

^

.reductionXor()

Bit-wise XNOR

^~ or ~^

^~ or ~^

n/a

generates:

~(x ^ y)

^~ or ~^

generates:

~(x ^ y)

Reduction XNOR

^~ or ~^

^~ or ~^

n/a

n/a

^~ or ~^

.reductionXnor()

Operator Name

Syncad

Verilog

VHDL

e

OpenVera

TestBuilder

Bit-wise OR

|

|

n/a

|

|

|

Reduction OR

|

|

n/a

n/a

|

.reductionOr()

Bit-wise NOR

nor

(any)

generates:

~(x | y)

nor

generates:

~(x | y)

|~

generates:

~(x | y)

Reduction NOR

~|

~|

n/a

n/a

~|

.reductionNor()

Bit-wise NAND

nand

generates:

~( x & y)

nand

generates:

~( x & y)

&~

generates:

~( x & y)

VHDL Bit-wise XNOR

xnor

generates:

x ~^ y

xnor

n/a

n/a

n/a

VHDL Bit-wise XOR

xor

generates:

x ^ y

xor

n/a

n/a

n/a

VHDL Bit-wise OR

or

generates:

x | y

or

n/a

n/a

n/a

VHDL Bit-wise AND

and

generates:

x & y

and

n/a

n/a

n/a

Operator Name

Syncad

Verilog

VHDL

e

OpenVera

TestBuilder

Logical AND

&&

&&

n/a

&&

&&

&&

Operator Name

Syncad

Verilog

VHDL

e

OpenVera

TestBuilder

Logical OR

||

||

n/a

||

||

||

Operator Name

Syncad

Verilog

VHDL

e

OpenVera

TestBuilder

Boolean Implication

=>

generates:

(!x) || y

generates:

(not x) or y

=>

generates: (!x) || y

generates:

(!x) || y

Boolean Event Check

now @

n/a

n/a

now @

n/a

n/a

Operator Name

Syncad

Verilog

VHDL

e

OpenVera

TestBuilder

Ternary

? :

(any)

? :

when else

? :

? :

? :

Operator Name

Syncad

Verilog

VHDL

e

OpenVera

TestBuilder

Delay

delay

#

transport or after

n/a

n/a

n/a