8.4 Generate Command Files for Third Party Simulators |
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8.4 Generate Command Files for Third Party Simulators |
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8.4 Generate Command Files for Third Party Simulators |
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8.4 Generate Command Files for Third Party Simulators |
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A command file for Verilog simulators can be generated for a project that will be simulated using a third party simulator. This file can be used when the third party simulator is invoked from the command line. TestBencher can also control the simulators graphically using the techniques described in Step 7: Setup External Simulators and Step 8: Simulate the Test Bench.
Generate the command file:
•Select the Project > Project Simulation Properties... menu option to open the Project Simulation Properties dialog. |
•In the Verilog tab, press the Generate Command File button to open a file dialog. •Enter the filename for the command file in the Filename edit box. (The file extension will be “.vc” by default.) •Click the Save button to save the file. |
Use the command file:
To use this file with a third party simulator, you will probably use the ‘-f’ switch followed by a space and then the filename entered above to simulate the project. For example, consider a project named test. If the generated command file is named ‘test.vc’ this file would be used with VeriLogger’s command line simulator using:
simx –f test.vc