VHDL Supported and Unsupported Constructs

The following is a comprehensive list of VHDL constructs translated by VHDL2Verilog.

Entity Declaration

Supported:

•Design with a single entity with architecture

•Entity ports: IN , OUT , INOUT , BUFFER , LINKAGE

•Interface element types:

•BOOLEAN

•BIT

•BIT_VECTOR

•STD_ULOGIC

•STD_LOGIC

•STD_ULOGIC_VECTOR

•STD_LOGIC_VECTOR

•INTEGER

Not supported:

•Interface element types:

•CHARACTER

•STRING

•REAL

•Design with no architecture

•Entity statements

Architecture Declaration

Supported:

•Multiple architectures for single entity declaration

•(Simple) Configuration declaration

Not supported:

•Design with an architecture and no entity

•Configuration specification

Packages and Package Bodies

Supported:

•Signal, Variable, Constant declaration

•Type declaration

•Subtype declaration

•Enumerated type declaration

•Component declaration

•Subprogram declaration

•Subprogram body (requires additional manual translation)

NOTE: Packages are translated only when used in a design!

Data Types

Supported:

•Signals/Variables/Constants of BASE subtype:

•integer

•real

•bit

•bit_vector

•std_{u}logic

•std_{u}logic_vector

•character

•string

•alias declarations

•Signal/Variable initialization

•to bit

•to vector

•to hex

•Subtype declarations with range constraint

Limited Support: 2D arrays of supported types

•1D arrays of supported types equivalent to arrays of bits up to 2D

•NOTE: for the above two cases, array types have to be CONSTRAINED.

•Enumerated type declaration

•Signal of enumerated type (state variable) translated to reg

•Enumerated types declared in a:

•Package

•Architecture

•Block

•Process

•Time types

•Record types

•Based literals (only base 2, 8, 10, 16)

Not supported:

•Unconstrained types

•Files

Generics

Supported:

•Generics of base type as described in Data Types with default expression

•integer

•real

•bit

•bit_vector

•std_{u}logic

•std_{u}logic_vector

•TIME

Not supported:

•Generics without default expression

Expressions

Supported:

•Expressions using signal and variables of types described in Data Types.

•Expressions with all VHDL supported operators:

•+, -, &

•AND, OR, XOR, NAND, NOR, XNOR (93)

•unary + and -

•*

•/

•MOD

•=, /=, <, >, <=, >=

•SLL, SRL

•** (power) operator (Only when used in a GENERATE statement)

•Qualified expressions

•Type conversions

•Function calls

•Aggregate primaries in an expression

Not supported:

•* * (power) operator (Except in generates)

•Allocator primaries

Sequential Statements

Supported:

•Wait statement (only in a process sequential body)

•Signal assignment

•with INERTIAL delay

•with TRANSPORT delay

•NULL assignment

•Variable assignment

•Assignment to an aggregate

•If statement

•Case statement

•Loop statement (FOR WHILE)

•Null statement

•ASSERT statement

•Procedure call statement

Not supported:

•REPORT statement

•NEXT statement

•EXIT statement

•RETURN statement

Concurrent Statements

Supported:

•Block statements

•Process statements

•Conditional signal assignments

•Selected signal assignments

•Component instantiation statements

•Generate statements

Not supported:

•Concurrent procedure calls

•Concurrent assertion statements

•Guarded signal assignments

Block statements

Supported:

•Declarative part:

•Type declaration

•Subtype declaration

•Constant declaration

•Signal declaration

•File declaration

•Component declaration

•Use clause (package)

•Statement part

•nested Blocks

•Process

•Concurrent assignment

•Component instantiation

•Generate

Not supported:

•Ports and port maps

•Generics and generic maps

•Guard expressions

Process Statement

Supported:

•Process variable declaration

•Process with sensitivity list

•Process without sensitivity list

•Process with a WAIT as the first or last sequential statement

•Process with an infinite wait at the end of a sequential body

•Process with a WAIT UNTIL at any place in the sequential body

•Edge-sensitive processes equivalent to Dffs

•Dffs with/without reset

•rising/falling_edge function

•'EVENT attribute

•'STABLE attribute

Concurrent Signal Assignments

Supported:

•Concurrent assignment with delay

•Concurrent assignment to an aggregate

•Concurrent assignment to a target with simple expressions in the range NOTE: in Verilog, the expressions have to be CONSTANT

•Conditional assignment

•Selected signal assignment

Not supported:

•Multiple waveform elements in a concurrent signal assignment

Component Instantiations

Supported:

•Generic Maps

•Generic mapping by ordered list

•Generic mapping by using formals and actuals

•Port Maps

•Port mapping by ordered list

•Port mapping by using formals and actuals

•Port aspect of component declaration different from the entity

•Scalar and vector OPENs

•2D arrays as ports

•Instantiation of components residing in the same file

•Instantiation of components residing in a package

Generate Statement

Supported:

•IF generate

•FOR loop generate

•Nested generates (FOR/IF)

•Identical labels in generate block and in block enclosing generate

•Component instantiations in generates

•Concurrent assignments in generates

•Processes in generates: regular, edge-sensitive (DFF-style)

Not supported:

•Declarations local to generate (block declarative items)

•Generates with loop parameters dependent on generics

Predefined Language Environment

Supported:

•NOW function

•Time type

•'RANGE, 'LENGTH, 'LEFT, 'RIGHT, 'LOW, 'HIGH, 'EVENT, 'STABLE, 'LAST EVENT attributes

Not supported:

•Other attributes

•TextIO