What if I have a question that isn't answered on this page?

If you run into a problem that does not have a solution on this page please send the following information, if available, to [email protected]:

•A detailed description of the problem, including under what circumstances the problem occu red, what version of the product you are using and on what platform you are using it.

•The log file: vhdl2v.log or v2v.log.

•The error message: cut and save the screen mesage to a file and attach it to your e-mail.

•The command line

•The input and output files

We will begin investigating the problem immediately, and respond to you as quickly as possible.

What does the -ssc switch do?

-ssc means Support Subprogram Call. It causes the translator to translate subprogram calls in the header only. You will see a verilog header in the <package_name>_package.verilog file, but no subprogram body. This is for the situations where some special functions are desired to be tranlsated manually.

I cannot find the std_logic_misc or std_logic_signed packages in your library. Do you provide it?

SynaptiCAD does not provide these packages. You can find them in many simulators, but some of the packages use v2v 's reserved words. The best way to work this out is to tailor the standard packages to your need. In most cases you only need a small part of the functions in the packages. You copy the standard package file to your own directory, delete the functions you do not need, and save it as your own file. Put this file name in the vhdl2v.map file instead of the standard package then do the translation. Even if the translator complains about the reserved words in the package, you can easily fix it because it is very small.

What does the -ssb switch do?

SSB stands for Support Subprogram Body. -ssb is an extension of -ssc. The translator translates the subprogram bodies as well as the headers. In this case, the whole package will be read in by the Translator even though only one or two functions in the package are used.

Does the tool append new information to <package_name>_package.verilog every time a new design file is converted, or is the existing package data in <package_name>_package.verilog overwritten with new data from the most recently converted file?

The new <package_name>_package.verilog will overwrite the old one, because each <package>.verilog is exclusively for the <output>.verilog file. The package is embedded to the <output>.verilog by an 'include statement.

Does the tool support the user naming the output file for converted packages to something other than the default <package_name>_package.verilog?

The tool cannot change the package name, but you can. Just rename the package file (or even edit it as you like), and change the corresponding name in the 'include statement in the <output>.verilog.

What should I do if I receive a Construct not supported warning message?

This warning message means that in your code you have used constructs that SynaptiCAD's Translator does not support at present time. This is because VHDL and Verilog cover different levels of abstraction, and some constructs in one do not have matching constructs in the other. In other words, "translatable" VHDL/Verilog is only a subset of standard VHDL/Verilog. Not all the constructs can be automatically translated. The tool will leave a comment in the place of the unsupported constructs in the output file to remind user to hand translate them. The major unsupported constructs are

•generics without a default value

•signal assignments with multiple waveforms

•unconstraint types and their attributes

•multidimensional accesses

•access type

•concurrent procedure calls

•TEXTIO procedures and functions

For a detailed list of unsupported constructs in VHDL and Verilog, please refer to the manual bundled with the software package.

What do the WARNINGs mean? Can I ignore them?

The warning messages mean that the resultant translation may or may not be correct. The warning messages remind you to check those lines of the translation to make sure they are correct. If you are sure, just ignore the warnings. If not, run the translation through a simulator to see if it complains about the indicated lines.

I received an error message during translation that I used a reserved word in my code. What does it mean?

SynaptiCAD's translator has a list of reserved words, such as "input" "output" "mod", etc, that can not be used as identifiers. The solution is to globally search and replace the reserved words you used with other names. A list of reserved words can be found in the Table of Reserved  Words and in the release notes.

What is function mapping?

The primary purpose of the function mapping file is to direct VHDL2Verilog on how it should process FUNCTIONs present in input VHDL.

It can be used to suppress printing of type conversion function calls widely used in VHDL. Most of the type conversions are not needed in Verilog, and VHDL2Verilog can read in a user-supplied function mapping file(s), and utilize information therein to create optimized Verilog output.

In addition, a function map file can be used to specify a replacement string that will replace all occurences of a function in the VHDL input. Each function can have its own string. It is assumed that the object specified by the replacement string exists.

How do I use function mapping files to direct the translation of a function?

When you translate a VHDL file, you can ignore VHDL functions or replace VHDL functions with the ones you specified. A function mapping file will tell the translator what functions should be ignored, or what functions should be replace. You can modify the function mapping file according to your requirements. When you perform the translation, add an option -fm mapping_file_name to the end of the command line.

For detailed information of using function mapping file, please refer to User's Manual.

General Questions

What if some of my comments are missing or misplaced in the translated version of my code?

We realize that our translators do not always preserve comments perfectly. This is because the translation is not line-by-line, so it can be difficult to place the comment strings in the resultant code. For example, the concurrent assignments in VHDL may be translated to Verilog in different order, so the translator may not be smart enough to decide if the comment should go with the first statement or the second one. Besides different syntax of VHDL and Verilog statements make it difficult for the tool to associate comments properly with the line before or after the comment.

The aim of the translator is to translate code from one HDL to the functional equivalent of the other (same simulation and synthesis results). The current version has an option to suppress all comments, which will solve your problem if the misplaced comments are merely an annoyance.

In the latest release several enhancements have been made to keep comments in place. We will keep working on the issue and users will see the further improvement gradually.