The following words are reserved in VHDL2Verilog and cannot be used in any of the input files. If one or more of the words below does occur, an error is flagged. The simplest method of working around use of a Verilog reserved keyword is to globally replace the word in the input VHDL source code and rerun the translation on the modified code.

always assign

buf bufif 0 bufif 1

casex casez cmos

deassign default defparam disable

edge else end endattribute endcase endmodule 

endfunction endprimitive endspecify endtable endtask event

force forever fork function

highz0 highz1

initial inout input

join

large

macromodule medium module

negedge nmos notif0 notif1

output

parameter pmos posedge primitive pull0 pull1 pullup pulldown 

rcmos reg release repeat rnmos rpmos rtran rtranif 0 rtranif 1 

scalared small specify specparam strength strong0 strong1 

supply0 supply1

table task tran tranif0 tranif1 tri tri0 tri1 

triand trior trireg vectored

wand weak0 weak1 while wire wor