Tool-specific attributes can be defined in the VHDL entity declaration to import pre­existing Verilog files. Currently, the framework of attributes provides support for full Verilog module import.

To import Verilog files in VHDL2Verilog, the user can define the attribute

VHDL2V_MODULE in the entity declaration. The type mark of this attribute needs to be of type STRING. Next, the attribute needs to be specified in the entity declaration. The expression in the attribute specification should also be a string. The pre-defined format of the string is explained below. Optional parts of the string in attribute specification are in italics.

( <file_to_read_from> ) (<begin_line>, <end_line>)

Spaces are ignored. It is an error to define multiple VHDL2V_MODULE attribute specifications. If begin and end line numbers for the file are not specified, the whole file is imported. If begin and end line numbers are specified, the line(s) starting from the specified begin line number till the end line number are read in.

For example, consider the following attribute definition and specification:

LIBRARY ieee;

USE ieee.std_logic_1164. all; 

ENTITY aha IS

PORT (SIGNAL s : OUT std_logic; 

      SIGNAL co : OUT std_logic; 

      SIGNAL a : IN std_logic; 

      SIGNAL b : IN std_logic; 

      SIGNAL c : IN std_logic);

attribute vhdl2v_module : string;

attribute vhdl2v_module of aha : entity is 

      "(/home/users/foo/verilog/demo.v) (1,20) "; 

END aha;

In the above example, because of the specification of attribute VHDL2V_MODULE, VHDL2Verilog will paste line 1 to 20 of file /home/users/foo/verilog/demo.v in the output file, instead of translating the given ENTITY and ARCHITECTURE description of aha to Verilog.

NOTE: No sematic, syntax or error checking is performed on the imported file. The same version that exists on disk is pasted in the output file.