The translation of DFF-equivalent processes is restricted to a few templates.

NOTE: edges can be rising or falling; for example purposes, the rising edge has been chosen.

The main templates are:

1.An equivalent PROCESS in Verilog will be created if the first or last statement in the PROCESS sequential body is found to match the WAIT statements below. The process should have NO sensitivity signals.

process

begin

  - one of the following wait statements:

  wait until rising_edge(clk);

  wait until (clk'event AND clk'last_value = '0');

  wait until (clk'event AND clk'last_value = '0' AND clk = '1'); 

  wait until (clk'event AND clk = '1' );

  wait until (NOT clk'STABLE AND clk'last_value = '0');

  wait until (NOT clk'STABLE AND clk'last_value = '0' AND clk = '1');

  wait until (NOT clk'STABLE AND clk = '1');

   -- can be any legal VHDL construct in the sequential body

end process;

For all these cases, output Verilog is:

always @(posedge clk) begin

// Verilog statement end

2.If the process has two sensitivity signals, and one sensitivity signal corresponds to asynchronous reset, and one to clock, and there is ONLY one IF-ELS IF-END-IF statement in the PROCESS sequential body, an equivalent Verilog process is created as follows:

process (reset, clk)

begin

  if reset = '1' then q <= '0';

     -- one of the following elsif expressions: 

       elsif rising_edge(clk) then

       elsif (clk'event AND clk'last_value = '0') then 

       elsif (clk'event AND clk = '1' ) then

       elsif (NOT clk'STABLE AND clk'last_value = '0' AND clk = '1')

   then

       elsif (NOT clk'STABLE AND clk'last_value = '0') then

       elsif (NOT clk'STABLE AND clk = '1') then

           q <= d;

       end if;

end process;

Output Verilog is:

always @(posedge clk or posedge reset) 

begin

   if (reset == 1'b 1)

        q <= 'b 0

   else

        q <= d;

   end

3.If the process has one sensitivity signal corresponding to clock and there is ONLY one IF-ELSIF-END-IF statement in the PROCESS sequential body, the PROCESS is mapped to an equivalent process in Verilog.

process (clk)

begin

   -- one of the following if expressions: 

     if rising _edge(clk) then

     if (clk'event AND clk'last_value = '0') then

     if (clk'event AND clk'last_value = '0' AND clk = '1') then

     if (clk'event AND clk = '1' ) then

     if (NOT clk'STABLE AND clk'last_value = '0') then

     if (NOT clk'STABLE AND clk'last_value = '0' AND clk = '1') then

     if (NOT clk'STABLE AND clk = '1') then

        q <= d;

     end if;

   end process;

 

Output Verilog is:

always @(posedge clk) 

 begin

    q <= d;

end

NOTE: All the above templates are also supported for Verilog negedge expressions (the 'clk' value being '0' instead of '1')