Functions (and procedure calls) can be translated (as opposed to being mapped) with the -tsb switch. Package bodies are not translated, so function declarations and bodies must be moved into an architecture for the tool to automatically translate them.

Subprograms that get called will be translated in the following manner:

...

FUNCTION foo (vec : std_logic_vector(7 DOWNTO 0)) return BOOLEAN; ...

If the above function is called in an architecture that is being translated, VHDL2Verilog will also create a file that contains the following Verilog code:

function foo;

 

input [ 7:0] vec;

begin

//

// *** INSERT THE TRANSLATED BODY HERE ***

//

end endfunction

If the body of the subprogram was available to the translator (e.g. in a PACKAGE BODY), the local signals, variables, constants, and local types will be translated as well.