Function Mapping and Translation

VHDL2Verilog allows users to  direct how it should process subprograms present in VHDL input files using function map files (*.fm files). Function map files are loading using the following command line syntax:

-fm file1 file2 ...

If any function map file is not found in the current directory, VHDL2Verilog will look in the %SYNCAD_HOME%/v2v/lib directory.

Function map files can be used to suppress printing of type conversion function calls widely used in VHDL. Most of the type conversions are not needed in Verilog, and VHDL2Verilog can read in one or more user-supplied function map files, and utilize information therein to create optimized Verilog output.

In addition, a function map file can be used to specify a replacement string that will replace all occurrences of a function in the VHDL input. Each function can have its own string. It is assumed that the object specified by the replacement string exists.

Mapping Functions Existing in VHDL Packages

Typically, subprograms are encapsulated in VHDL packages. An example of such a package is the IEEE Standard STD_LOGIC_1164 package. Information about mapping of functions declared inside packages is supplied via the function mapping file. The function mapping file is an ASCII file with format as shown below:

// Comments and empty lines are ignored

// Each entry in the file should have 5 fields 

//  1      2                 3                  4           5

// Library Package           Function           Argument    Action

    IEEE   std_logic_1164    To_bit               1         ignore

    IEEE   std_logic_1164    To_StdULogicVector   1         -

    IEEE   standard          now                  $time     replace

 

The fields are: 

1. Library :

•SYNTAX: identifier

•This field states the library.

2.Package :

•SYNTAX: identifier

•This field states the package name; if the file in which the package resides is not <package name>.vhd, the mapping of package name to file needs to be specified in the 'vhdl2v.map' file.

3.Function :

•SYNTAX: identifier

•This is the name of the function that needs to be ignored or replaced.

4.Argument :

•SYNTAX: integer_number | string | "-"

•The argument can be any character or character string. Based on the Action field entry (Field 5), the character string is interpreted as an integer (Action entry is "ignore" or "-") or a character string (Action entry is "replace").

•If the argument is interpreted as an integer, this denotes the function parameter that needs to be printed in the output Verilog. The parameter to be printed is specified by giving the argument number. If this field contains '-', the argument defaults to '1'. It is an error if the function does not have the argument specified.

•If the argument is interpreted as a string, this string will replace ALL occurrences of the function in the output Verilog.

5. Action :

•SYNTAX: "ignore" | "replace" | "change" | "-"

•VHDL2Verilog will ignore the function, and print only the specified argument in the output file if the entry is ``ignore'' or ``-''. If the entry is ``replace'', the specified string will replace all occurrences of the function and drop all the arguments. If the entry is ``change'', the specified string will replace all occurrences of the function and keep all the arguments.

Default Function Map Files

Function map files for popular packages are available in the software distribution in the %SYNCAD_HOME%/v2v/lib directory and loaded by default when the translator is run. These files are not loaded by default when a user-specified function map file is passed on the command line using the -fm option, but they can still be loaded by adding them to the command line arguments.

Mapping Functions in VHDL Input

Functions not declared in packages can be mapped by attaching VHDL2Verilog specific attributes in the architecture of the input VHDL source file. The two attributes and attribute specification that need to be defined in an architecture block declaration are as follows:

For printing a specified argument, use:

attribute vhdl2v_function_action : string; 

attribute vhdl2v_function_argument : integer;

attribute vhdl2v_function_action of function_name : function is "ignore";

attribute vhdl2v_function_argument of function_name : function is 1;

 

In the above case, VHDL2Verilog will ignore the printing of the function name, and only print the 1st argument of the function call.

For replacing a specific function, use:

attribute vhdl2v_function_action : string; 

attribute vhdl2v_function_argument : string;

attribute vhdl2v_function_action of function_name : function is "replace";

attribute vhdl2v_function_argument of function_name : function is "whatever";

 

In the above case, string ``whatever'' will replace all occurrences of functions_name.