BugHunter Pro and the VeriLogger Simulators

9.3 Mapping VHDL packages to file locations

9.3 Mapping VHDL packages to file locations

Previous topic Next topic  

9.3 Mapping VHDL packages to file locations

Previous topic Next topic  

Translating files that reference VHDL packages

You must specify the location of packages being used by the input VHDL file. By default, VHDL2Verilog looks in the current working directory for the filename <package_name>.vhd, and if the file is not found there, in $SYNCAD_HOME/v2v/lib/<package_name>.vhd.

However, the user can create a file vhdl2v.map in the current directory, and specify the mapping of VHDL packages to the physical file location. The vhdl2.v file can be manually created or automatically created with the mapmaker utility.

Manually mapping packages to package files with vhdl2v.map file

vhdl2v.map is an ASCII file with format as shown below:

// This is a comment

// Package name  Name of file containing package

functions        $SYNCAD_HOME/v2v/lib/functions_header.vhd

numeric_std      $SYNCAD_HOME/v2v/lib/numeric_std_header.vhd

my_package       mine.vhd

bscmp            ibuf_pack.hdl

`//' or `#' as the first character(s) of a line denotes a comment. Everything following the comment will be ignored. A mapping line should contain two fields. The first field is the package name exactly as used in the VHDL file, and the second field is the complete path to the physical location of the VHDL file containing that particular package.

The delimiter between the two fields can be a space, tab or a combination of the above. Previously defined environment variables can be used to specify pathnames.

A default map file can be found in the $SYNCAD_HOME/v2v/lib directory. Usually, the user would copy this default map file to the current directory and modify it as necessary.

On NT the following syntax is valid as well (i.e using %% for variables and \ instead of / for hierarchical separators):

functions    %SYNCAD_HOME%\v2v\lib\functions_header.vhd

Using Mapmaker Tool to automatically generate a vhdl2v.map file

VHDLl2Verilog comes with an automated tool, mapmaker, to help you quickly create map files.  At a command prompt, run mapmaker with the list of your source files, and it will generate a vhdl2v.map file in the current directory which contains mappings for all of the packages in those source files, plus the default mappings. You can also manually add additional mappings to the map file created by mapmaker.

Syntax:

mapmaker.exe {-d pathname} <list_of_VHDL_files>

Arguments:

The '-d' option is used to specify the output directory for the 'vhdl2v.map' file.

The list of VHDL files is scanned for packages. If a package is found,an entry is made in the 'vhdl2v.map' file.

NOTE: VHDL-87 files need to be preceded by the '-87' switch (VHDL-93 is default).

NOTE: VHDL-93 files need to be preceded by the '-93' switch if '-87' switch was used previously on that line.