Known issues with VHDL2Verilog

1. DR 550

•Description: Overloaded VHDL functions cannot be discerned during function mapping. The problem comes about due to the fact that the function mapping takes into account only the name of the function.

15. DR 583

•Description: In a design that uses packages, the comment header from the package file frequently gets printed in the main output file instead. No known workaround exists.

16. DR 621

•Description: Real Delay values are translated into exponential values.

•Workaround: Manually change the delay values to reals again. For example: # (1. 90000 0e+0 0) can be changed to #1. 9.

17. DR 720

•Description: In entities with generates parameterized by generics, the generates are elaborated only for the default value of the generic(s). Hence, if the entity is instantiated with a generic value other than the default, the translation will not be correct. NOTE: this problem applies ONLY to the entities with generates.

•Workaround: Replicate the problematic entity so that there is a separate entity declaration for each used value of the generic.

18. DR 724

•Description: If different default values for a generic are specified in the entity and component declarations, vhdl2v takes the one in the entity, whereas it should take the one in the component declaration.

•Workaround: Make sure that the entity declaration uses the proper default value of the generic.

19. DR 788

•Description: An aggregate constant is translated to a concatenation. Example:

TYPE WSizeTableType IS

ARRAY(INTEGER RANGE 1 TO 13) OF INTEGER;

CONSTANT TcWSizeTable: WSizeTableType :=

(7, 9, 11, 13, 15, 17, 19, 21, 23, 25,

27, 29, 31);

translates to:

parameter TcWSizeTable = { 7, 9, 11, 13, 15, 17, 19, 21, 

      23, 25, 27, 29, 31};

•Workaround: No easy workaround known. One has to manually change the Verilog output according to the design intent.

20. DR 848

•Description: Based numbers and octal and hex bitstrings in OTHERS are not correctly translated. Example:

sig_array16 <= ( OTHERS => 16#c# );

is translated to:

{sig_array16[ 3] , sig_array16[ 2] , 

        sig_array16[ 1], sig_array16[ 0]} = {(3 - 0 + 1){}};

// the literal disappears

•Workaround: Use bit string literals in aggregates with OTHERS

21. DR 765

•Description: No support for GUARD expressions. The GUARD expression, if present in the block declaration, has special meaning in the case of VHDL guarded conditional signal assignments.

•Workaround: The conditional signal assignment is equivalent to a VHDL
signal assignment if the GUARD expression evaluates to true. Consider:

ARCHITECTURE ... BEGIN

test : BLOCK (reset != '1') IS BEGIN

a <= GUARDED '1'; END BLOCK;

END ARCHITECTURE;

is the same as

ARCHITECTURE ... BEGIN

PROCESS(reset)

BEGIN

if (reset != '1') THEN a <= '1';

end if;

END PROCESS;

22. BZ 19: Issue with translation of state machines

•Description: In the the .vhd file there are multiple declarations in which state name ‘idle’ appears. For example

type firststate is (idle, notidle) etc

type anotherstate is (idle, notsoidle) etc.

The translator defines a parameter in Verilog for each. In some cases, the name for common parameters (idle) gets mixed up in the output Verilog file. When there are assigned in the output fileTranslator mixes up these definitions and picks up the last definition of idle.

•Workaround: Modify the input file and rename the type definition. In the example, the new declaration could be-

type firststate is (idle, notidle) etc

type anotherstate is (idle1, notsoidle) etc.

Note than name ‘idle’ in anotherstate is changed to ‘idle 1’.