The VCD format is a standard Verilog file format that can be used with external waveform viewers, static timing analyzers, or VeriLogger's graphical display. Watched signals in VeriLogger are displayed graphically, and by default are NOT dumped to a VCD file. Two check boxes in the Project Simulation Properteis dialog control the output of data gathered by watched signals.
BugHunter also supports saving simulation results into a compressed binary timing diagram format (the BTIM format). This format is used by default for saving off the waveform results of simulations. BTIM files are typical 200-1000x compressed compared to an equivalent VCD file. This means that dumping to a BTIM file instead of a VCD file will enable a simulation to run quicker, because less file IO is required to save the data. BTIM dumping capability is enabled via a PLI application that is passed on the simulator command line when it is launched, so it is also possible to create BTIM files when running a simulation standalone without the BugHunter graphical debugger. Just as there are system tasks for creating VCD files (e.g. $dumpvars), there are similar system tasks that can be placed into Verilog source code to manually generate BTIM files.
To determine the output of watched signals:
•Press the Project Simulation Properties button or choose the Project > Project Simulation Properties menu to open the dialog. |
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•Check the Capture and Show Watched Signals checkbox to view watched signals in the Diagram window. Saving the resulting timing diagram will save a BTIM file. •Check the Dump Watched Signals checkbox to insert a $dumpvars statement into the test bench code that will dump data from watched signals to a VCD file. |
To import and view a VCD file:
•Select the Export > Import Timing Diagram From menu option. This Open dialog is special in that it remembers the file type of the last file imported. •Type the name of the VCD file you wish to open in the File name: edit box. •Click the Open button to load the file. The waveforms are now visible in the Diagram window. |
If you are using Verilog, VCD files can also be generated by using the Verilog system tasks $dumpvars, $dumpfile, $dumpall, $dumpon, and $dumpoff to save waveform data. See the Verilog Language Overview for more information on the syntax of these statements.