The Verilog model of your system created by WaveFormer can also be simulated by traditional Verilog simulators. The complete verilog model simulated by WaveFormer is composed of (1) the verilog file generated by WaveFormer (untitled.v for this tutorial), (2) the WaveFormer library file wavelib.v, and (3) any external model files you have included (e.g. sram.v for this tutorial). Follow the instructions of your Verilog simulator to simulate these files together.