To demonstrate how to make changes to a Verilog source file inside WaveFormer, we will edit the SRAM model file sram.v in the Report window:

1. Change line 18 from: ram[i] = 0; To ram[i] = 8;

This causes the SRAM cells to be initialized with 8 instead of zero.

2. Select the Report > Save Report Tab menu option to save your change.

Let's see the effect of this change:

3. Press the Simulate Once button in the Signal Properties dialog, or move an input edge. Either of these steps initiates a resimulation.

You may have anticipated that DBUS would now show 8 (we did when we first did this tutorial!), but it is correct in showing 808 because our DBUS is a 16-bit value composed of the data in two parallel SRAMs each initialized with 08 (hence 0808 = 808).

4. Reset the line back to ram[i] = 0;