11.1 Verilog |
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11.1 Verilog |
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11.1 Verilog |
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11.1 Verilog |
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This section lists the files generated for pure Verilog models. Combination projects using Verilog and the C++ TestBuilder library are covered in the TestBuilder section. Some advanced features like Transaction Manger generation, random constrained data generation, and advanced data structures are supported using the combined TestBuilder and Verilog languages.
Files needed for simulation:
•projectName.v - contains top-level module for project. This is the Transaction-Level Model, TLM, file (the expanded template file). •One timing transaction file for each timing diagram in the project: projectName_diagramName.v - contains transaction module. •All of the MUT files listed in the User Source Files folder in the Project window. •syncad.v - contains base constants that are used throughout the generated code. •wavelib.v - (optional) contains register and latch module definitions that are used by timing diagrams with clocked “Simulated” signals. If there are no clocked simulated signals in the entire test bench then this file is not needed. •Library files - When a new project is created a lib/verilog directory is created in the project directory that contains various modules that may or may not be used by the project. Currently, these libraries consist of different clock models that are used based on the types of output clocks used in the timing diagrams. •projectName_emulator.v - (optional) If using a reference model (see Section 9.3 Golden Reference Models) then a file named projectName_emulator_skeleton.v is generated and placed in the Associated Files folder for the Transaction-Level Model. This file should be copied to another file named projectName_emulator.v, placed into the User HDL Files folder and modified to represent the reference model. •tb_projectName_tasks.v - (optional) If using File I/O then this file will be generated and added to the Associated Files folder for the Transaction-Level Model. •tb_libraryName_user_classes.v - (optional) one file is generated for each imported (Non-default) library in the project hierarchy. All of these library packages are placed in the Associated Files folder for the Transaction-Level Model of the top level project during test bench generation. |
Accessing Project Level Variables from a Diagram in Verilog
In Verilog, only variables that are instances of user defined classes are accessible from the diagram. In these cases, the variable is just referenced by its name. An upward search through the scopes will be done to find the variable instance. For example, if you had an ATMCell class definition and an instance named cell either at the project-level or the diagram-level, then you could access the HEC field of cell by using cell.HEC syntax.
Data Packing in Verilog
When packing is enabled for at least one field of a class definition, that class will have an additional field that is an array of bytes which is used during packing operations. This array is called packed_array. The pack task will pack the fields to packed_array. The unpack task will fill the data fields of the class with data from packed_array. For example, if you had a variable named VAR0 that was an instance of a class definition with fields that had packing enabled, you would call VAR0.pack to pack those fields into VAR0.packed_array. This byte array could then be accessed by an index to drive a signal. If you were reading data from a bus you would use Sample(s) to store the data one byte at a time into the packed_array. Then once you were done reading, you would call VAR0.unpack to convert the data to its class form.
Third Party Simulators
When you launch a third party simulator from the command line, you may need to specify that there are two top-level modules created by TestBencher. The first is tbench which contains all of the transaction code. The other module is tbsyslog which contains the code for logging errors and warnings. If you are launching the simulator from within the GUI environment, then this will automatically be handled. Also SynaptiCAD's command line simulators are smart enough to detect that there are two top level modules and set the design up automatically.