5.3 Pause Simulation Marker (Verilog Only) |
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5.3 Pause Simulation Marker (Verilog Only) |
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5.3 Pause Simulation Marker (Verilog Only) |
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5.3 Pause Simulation Marker (Verilog Only) |
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A Pause Simulation marker will pause the entire simulation when it reaches the marker. This marker is like a graphical breakpoint. While the diagram is paused, you can check variables and signal states. When you are done, use your simulator run button or run command to continue the simulation.
This feature is not supported in VHDL because there is no language construct that can stop the simulator. However, some simulators can be configured to pause on assert failures. If your simulator supports this feature, then you can use an HDL code marker to place an assert in the timing diagram (see Section 5.6 HDL Code Marker).
To specify a Pause Simulation marker:
•Add a marker to the timing diagram. The marker will pause all processes in the entire model. |
•Double-click on the marker to open the Edit Time Marker dialog. •From the Marker Type drop-down list, choose Pause Simulation (Verilog only). |
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