6.13 Language Independent Types

SynaptiCAD has defined a set of language independent types that is used by TestBencher's graphical interface in place of the native types for a given language. This is done to facilitate the development of language independent class definitions and variables. During test bench generation, the language independent type is converted to the appropriate native type for the language being generated. Not all of the language independent types are supported by all of the generation languages. The dialogs that allow selection of these types, such as the Class Definitions & Variables dialog, will only display the language independent types that are supported for at least one of the currently licensed languages. Additionally, these dialogs support a view that will display only the items that are available for the currently selected language.

Description of SynaptiCAD Language Independent Types

SynaptiCAD Type	BitSize	Description/Values
bool	1	Truth values (1 or 0)
2_state	1	0, 1
2_state_vector	variable	0, 1 in vector format
byte	8	Unsigned integer represented by 8 bits
int	32	Signed integer represented by 32 bits
unsigned_int	32	Unsigned integer represented by 32 bits
real	64	Floating point numbers
fixed_len_string	variable	Series of characters enclosed by quotes
variable_len_string	n/a	Series of characters enclosed by quotes
time	64	Simulation time quantities
4_state	1	0, 1, X, Z
4_state_vector	variable	0, 1, X, Z in vector format
event	n/a	Synchronization item
std_logic	1	U, X, 0, 1, Z, W, L, H, -
std_logic_vector	variable	U, X, 0, 1, Z, W, L, H, - in vector format
std_ulogic	1	Unresolved version of std_logic
std_ulogic_vector	variable	Unresolved version of std_logic_vector
signed_logic	variable	Signed version of std_logic_vector
unsigned_logic	variable	Unsigned version of std_logic_vector

Type Conversion

The chart below provides conversion information for converting between the language independent types and the generated language native types. Cells that are grayed out represent items where no conversion is available between the language independent type and the native language types.

SynaptiCAD	Verilog	VHDL	TestBuilder
bool	reg	boolean	bool
2_state	reg	bit	tbvSmartSignal2StateT
2_state_vector	reg	bit_vector	tbvSmartSignal2StateT
byte	reg	bit_vector	tbvSmartSignal2StateT
int	integer	integer	tbvSmartIntT
unsigned_int	integer	natural	tbvSmartUnsignedT
real	real	real	tbvSmartDoubleT
fixed_len_string	reg	string	char[]
variable_len_string			tbvSmartStringT
time	time	time	N/A
4_state	reg	std_logic	tbvSmartSignal4StateT
4_state_vector	reg	std_logic_vector	tbvSmartSignal4StateT
event	event
std_logic		std_logic
std_logic_vector		std_logic_vector
std_ulogic		std_ulogic
std_ulogic_vector		std_ulogic_vector
signed_logic		signed
unsigned_logic		unsigned
actel_current_delta	reg	std_logic
actel_temperature	reg	std_logic
actel_voltage	reg	std_logic
actel_voltage_common	reg	std_logic
actel_voltage_delta	reg	std_logic

Note that not all language types are perfectly equivalent to the SynaptiCAD type. Variances are as follow:

•Verilog reg type is a four state type.

•Verilog integer type is signed.

•VHDL natural is a limited version of the VHDL integer type, so it’s max value is 2^31, not 2^32.

•Some languages do not provide an unsigned integer type.