This chapter covers advanced project level features including sub-projects, golden reference models, and properties that effect the code generation. Sub-projects are TestBencher projects that are contained within other projects, allowing complex test benches to be developed and verified in an incremental manner. Sub-projects also provide an easy interface for multiple port testing.

TestBencher can also generate a C++, VHDL or Verilog Golden Reference model that runs in parallel with the VHDL or Verilog Model Under Test. During simulation, transactions are sent to both the MUT and the reference model. The results from the two models are then compared.

Right-mouse click on any element in the project tree to reach the context sensitive menu that provides a list of actions that can be performed for that element. Many elements have Properties dialogs that can be reached through the context menus and Project menu functions.