Verilog2VHDL Release Notes: Software Version 6.0 May 2007

Changes in current version (6.0)

1.Added ‘pragma translate_on’ and ‘pragma translate_off’ to the list of synthesis directives, in addition to the existing ones (BZ 10)

2.Added a new switch –no_header. This switch will not print a header in the output file.

3.Made enhancements to the comment placement, to make output file similar to input.

4.Enhanced documentation. New documents added include- quick start guide, a summary of known bugs and workarounds, a brief document on recommended modeling style.

Changes in version 5.6

1.Improved Verilog pre-processor. It can process Verilog file with unlimited size. It is now able to process "defines" with empty macro.

2.The readability of the VHDL output is dramatically improved. The improvements includes proper indentation, better comment positioning, and consistent spacing between statements.

3.The unnecessary type conversion functions are eliminated. The previous version of the tool widely used type conversion functions. In some situations, these type conversion functions are not necessary, although they don't affect the functionality of the output. These unnecessary type conversion functions are eliminated in the new release so that the output code is functional and clean.

4.Shift operations and condition operations in parameter declarations are now supported.

5.License utility is upgrade in this version. The license daemon and utility distributed with the new release is version 8.2.

Changes in version 5.5

1.A new option, "-vpp", is added for integrating Verilog pre-processing. When set, this option instruct the translator to pre-process the Verilog source file, elaborate compiler directives such as "ifdef", "include", etc, and generate an Intermediate File (IF). The translation then proceeds on the intermediate file.

2.A new option, "-an", is added to allow users to rename the generated VHDL architecture. The default name of the generate architecture is "VeriArch".

3.The library name for the packages provided by SynaptiCAD is renamed. The original name was "Verilog". The new name is "ASC".

4.Indentation of the output VHDL code is improved. 5. Library  files provided with the translator are revised and upgraded.

Changes in version 5.0

1.The option “-mrv” is re-defined. This option improves the translation of blocking statement without putting “wait for 0 ns” after each translated statement.

2.Verilog POSEDGE/NGEDGE event controls are translated into standard VHDL edge functions : rising_edge/falling_edge, instead of the functions provided by the tool. It increases the compatibility and synthesizability of the translated code.

3.A bug in provided library files is fixed.

4.A bug in translating definition of variables is fixed.

Changes in version 4.4

1.The distributed package now includes both VHDL2Verilog and verilog2vhdl translator. They are licensed separately.

2.Using signals as delay parameters is supported.

3.A bug in Verilog for-loop is fixed. The translation could be wrong when increment of for-loop is other than 1.

4.A bug on type conversion function is fixed.

5.More ternary functions are added to the library file functions.vhd.

6.A bug in Verilog if-else statement is fixed. The sequence of translated VHDL elsif could be wrong in some cases.

7.Support of test bench translation is improved. A few bugs on FILE I/O translation are fixed.

Changes in version 4.3

1.Case statements with constant expressions are supported. In Verilog, it is possible to use a constant expression for case expression and match the value of the constant expression against case items, while it is not allowed in VHDL.

2.The defparam statements will not be validated if option "-nc" is used. It will allow user to continue the translation without error even if some instance modules are not available.

3. More functions are added to the library file utils.vhd.

Changes in version 4.2

1.SynaptiCAD's products now use FLEXlm License Manager.

2.The verilog2vhdl and VHDL2Verilog are now two features of one SynaptiCAD tool -- V2V translator. The directory structure of V2V translator is different from the old verilog2vhdl or VHDL2Verilog structures.

3.The environment variables $V2 V_HOME and $VHDL2V _HOME (for VHDL2Verilog translator) are merged into a new environment variable $ASC HOME.

4.Y2K compliant.

5.Improved Verilog pre-processor(vpp) to provide better support for 'define, 'include and 'ifdefs/ifndefs.

Changes in version 3.3 :

5.verilog2vhdl translator now uses Elan License Manager.

6.Two versions of buffers.vhd package - for synthesis and simulation - were merged into one.

3. New -Map_Registers_to_Variables (-mrv) switch allows to translate Verilog registers to VHDL variables. By default, registers are translated to signals. Existing restrictions on using -mrv switch:

oAll parameters to tasks/functions have to be passed explicitly

oAll inout/output task enabling arguments have to match the respective declared task arguments by size

oConcatenations as inout/output parameters to tasks and functions are not supported

4. A beta-version of a Verilog pre-processor (vpp) is included in $V2V_HOME/bin. This pre-processor is built using the GNU gcc. 'vpp' fully supports `defines, `includes, and `ifdefs/ifndefs. Usage is vpp input_file [output_file] . If no output file is specified, output goes to stdout.

Suggested usage:

vpp input_f ile.v temporary_f ile.v

v2v temporary_f ile.v temporary_f ile.hdl [v2v switches]

5. Instance names of Verilog primitive gates are preserved as the equivalent assignments' labels.

1.TERNARY functions in functions* .vhd packages were modified to comport with the behavior of the ? operator for X and Z values of the conditional expression, as defined in Verilog LRM.

2.Support for translation to VHDL std_ulogic types was removed. Now, only std_logic types are supported.

3.Support for ranges in parameter declarations was added.

4.A switch - Preserve_order to keep the order of concurrent statements the same as it was in the input Verilog file was added.