Known issues in verilog2vhdl

1. DR 465

•Description: Non-integer values of time_precision in `timescale compiler directive are not translated.

•Workaround: reduce the time resolution off the `timescale directive so that all values are integers. Example:

`timescale 1.5ns/150ps can be rewritten as

`timescale 1500ps/150ps

2. DR 486

•Description: $readmem calls with only ONE (start) address specified are not always translated correctly.

•Workaround: always specify both the start and the finish addresses for the system task call. Example:

parameter word_length = 8,

mem_size = 8;

reg [word _length-1:0] mem [ 0:mem _size-1]; ...

$readmemb("mem.dat", mem, 3); // this will NOT translate correctly

// modify the $readmemb call to

equivalent

$readmemb("mem.dat", mem, 3, mem _size-1); // this will translate correctly

3. DR 488

•Description: Addresses other than integer (i.e. hex and oct) are not supported for $readmem calls.

// This call will generate an error message

$readmemb("mem.dat", mem, 4'h2, 4'hB);

•Workaround: Specify all addresses for $readmem calls in integer format

4. DR 504

•Description: Memories used in concatenations on the left hand side of assignments do not get expanded to bits

Example:

reg[ 7:0] RL[ 1:8];

reg[ 7:0] RH[ 1:8];

reg[ 7:0] E[1:8];

integer ADDRESS;

...

{E[ ADDRESS] ,RH[ ADDRESS] ,RL[ ADDRESS] } = DEC_READ (ADDRESS);

 

translates to:

 

TYPE MEMORY _0 IS ARRAY (1 TO 8) OF std _logic _vector(7 DOWNTO 0);

SIGNAL E, RL,RL : MEMORY _0 REGISTER ;

(E(ADDRESS), RH(ADDRESS), RL(ADDRESS)) <= 

              std _logic _vector' (DEC_READ(REG, E, RH, RL));

 

which is incorrect VHDL syntax.

•Workaround: Use a temporary vector to accommodate the return value of DEC_READ(ADDRESS), and then assign parts of the vector to corresponding memories.

5. DR 676

•Description: Case statement with non-constants as case item expressions translates to VHDL case statement with illegal syntax. Example:

reg a;

case (1'b1)

a : d = boo[ 0]; default : d = boo[ 3];

translates to: BEGIN

CASE '1' IS

WHEN a => -- wrong VHDL syntax

V2V_d <= to_stdlogic(boo(0));

WAIT FOR 0 NS; WHEN OTHERS =>

V2V_d <= to_stdlogic(boo(3));

WAIT FOR 0 NS; END CASE;

•For such cases, verilog2vhdl will print a warning, so that either Verilog input or output VHDL can be easily fixed manually.

6. DR 685

•Description: In certain cases, translations of ternary operators with integer arguments produce wrong outputs during simulation if other arguments to the operator assume values X or Z.

7. DR 692

•Description: Translation of registers to variables (- Make_Registers_Variables switch) does not work for tasks which do not have all parameters explicitly declared. Example:

task dummy3;

// this task uses global addressing

// including global referencing of parameters to a procedure call begin

s3 = a ^ b ;

dummy2(a, b, c, s4, out3);

end

endtask

•Workaround: Always specify all parameters to tasks explicitly if you want to use -mrv functionality

8. DR 695/697

•Description: Function calls and task enables where actual parameters do not match formal parameters in size are not translated correctly. In such cases, verilog2vhdl will automatically resize the formal parameters with a size conversion function, which cannot be passed as an output or inout parameter. The same will happen if the actual parameter to a function call/task enable is a concatenation. Example:

task MAX;

inout [ 3:0] first; input [ 3:0] second; begin

if (first < second) first = second;

end

endtask

...

reg [7:0] a, b; MAX(a, b);

translates to:

PROCEDURE MAX (SIGNAL first : INOUT

std _logic _vector(3 DOWNTO 0) BUS;

second : IN std _logic _vector(3 DOWNTO 0))

IS

BEGIN

IF first < second THEN

first <= second; WAIT FOR 0 NS; END IF;

END;

SIGNAL a, b : std _logic _vector(7 DOWNTO

0);

MAX(to_stdlogicvector(a, 4),

to_stdlogicvector(b, 4));

•Workaround: Always make sure that formal and actual parameters of tasks and functions match in size.

9. DR 696

•Description: Subprogram calls made from within other subprograms may result in mismatches between formal and actual parameter classes, e.g. a variable may be passed when a signal is required.

10. DR 698

•Description: The Verilog preprocessor supplied with verilog2vhdl for the purpose of providing support for compiler directives presently is in beta version, and does not have any user messaging whatsoever. Usage:

vpp <input_file><output_file>

11. DR 771

•Description: Translations of decimal constants are not sized properly in concatenations. Example:

reg [ 19:0] a;

...

a = { 10'd0, 10'd0};

SIGNAL a : std _logic _vector(19 DOWNTO 0) REGISTER ;

...

a <= std _logic _vector' (0 & 0); -- wrong translation

•Workaround: Use binary constants instead of decimal.

12. DR 911

•Description: Verilog identifiers differing only in case are not resolved. Example:

reg a; 

reg A;

will both correspond to

signal a : std _logic;

•Workaround: Make sure that your source does not contain such identifiers.

13. DR 953

•Description: In some rare cases, verilog2vhdl will put entities in the output VHDL file in the wrong order, i.e. an entity will be instantiated before defined in the file.

•Workaround: Manually fix the order of entities in the output VHDL file.

14. BZ 21: Problems while translating functions in the output file

•Description: Translator gives an error while translating function from Verilog to VHDL.

•Workaround: Function MUST be declared before it is used in the input Verilog file. Please move the function to the top of the module declaration before translating.