If your design works on one simulator but is failing with another simulator, a race condition is a likely cause of the error. Races can occur in Verilog simulations because the Verilog Language does not fully specify event ordering between concurrent processes in a design, so this ordering will  vary vary between simulators. This was intentional, as a valid design should not rely on a particular ordering of these events, but it's very easy to introduce a race in a design if Verilog coding standards aren't strictly followed.

When you want to check for race conditions in your code, VeriLogger supports several options that can be used to change the event queue order. If your design passes with one ordering, but fails with another, this indicates there is probably a race condition in your design. If this happens, the optional waveform comparison feature can be useful in pinpointing the location of the race condition.

Options changing event queue order (supports race detection):

--scd_invert_queue

Inverts default order of executed processes.This option may negatively impact simulation speed, so it should only be used when checking for races.

--scd_randomize_queue

Randomizes default order of executed processes. This option may negatively impact performance, so it should only be used when checking for races.

--scd_mtilike_queue

Executes events in similar order as ModelSim does. This option is particularly useful if you have a design that passed on ModelSim and is failing on other simulators and you're trying to determine if the problem is a race.

Modelsim-compatibility options:

+mti_compat

Enables all three ModelSim compatibility options (--scd_mtilike_dist_functions, --scd_mtilike_queue, --scd_immediate_sensitivity).

--scd_immediate_sensitivity

Makes Verilog event control statements at the beginning of a process immediately sensitive after simulation initialization. This option will generally be used in combination with the --scd_mtilike_queue, in order to match ModelSim's operation as close as possible.

An example of an event control at the beginning of a process is a statement like:

always @(posedge CLK)

 

--scd_mtilike_dist_functions

Enables ModelSim compatibility for the Verilog system functions that control random number distribution ($dist_ functions).