(TBench) 1.4 Signal Data Types and VHDL user defined types

SynaptiCAD's tools use a language independent signal type so that one timing diagram can generate code for both VHDL and Verilog test benches. Double click on a signal name to open the Signal Properties dialog and the Signal Type box shows the signal's type. Below is a table that shows the translation between the types.

SynaptiCAD	Verilog	VHDL
4_state	reg	std_logic
4_state_vector	reg	std_logic_vector
bool	reg	boolean
2_state	reg	bit
2_state_vector	reg	bit_vector
byte	reg	bit_vector
int	integer	integer
unsigned_int	integer	natural
real	real	real
fixed_len_string	reg	string
variable_len_string
time	time	time
event	event
std_logic		std_logic
std_logic_vector		std_logic_vector
std_ulogic		std_ulogic
std_ulogic_vector		std_ulogic_vector
signed_logic		signed
unsigned_logic		unsigned
actel_current_delta	reg	std_logic
actel_temperature	reg	std_logic
actel_voltage	reg	std_logic
actel_voltage_common	reg	std_logic
actel_voltage_delta	reg	std_logic

The Signal Type box also supports VHDL user-defined types that can be directly entered into the box. By default all signals are assumed to have a type of std_logic and a direction of out (CLK0, SIG0, and VirtualBus will use the defaults for this tutorial). In this section you will add SIG1 and SIG2 to demonstrate signals with a standard integer type and a user defined type.

Add SIG1 and SIG2

•Click on the Add Signal button two times to add two signals.

add_signals

•Press the VAL button two times (not a double click). The first click selects Valid as the initial graphical state, and the second click selects Valid as the toggle state (as indicated by the red T). This causes the VAL button to stay selected when you draw waveform segments.

•Sketch some valid waveforms for SIG1 and SIG2 similar to those in the figure below.

diagram3-hdlStimulus-drawnValidSegments

Change the type of SIG1 to integer and add values to the waveform:

•Double-click on the SIG1 signal name to open the Signal Properties dialog.

•Choose integer from the Signal Type box.

•Choose dec from the Radix box to indicate that the values you will be entering into the virtual state are decimal values.

•Press OK to close the dialog.

sig1_properties_dlg

•Double-click on the first waveform segment on SIG1 to open the Edit Bus State dialog.

•Enter integer values for each segment (we used 25, 50, 47). Use the Next button to move between segments.

sig1_waveform

Change the type of SIG2 to MyColor and add values to the waveform:

Next we will add a user defined data type called MyColor. For a real VHDL simulation, the user defined type and the color value of the waveforms would have to match the code in the model under test. For instance, MyColor might be defined as: enum MyColor ={RED, GREEN, BLUE, BLACK} in the model under test code.

•Double-click on the SIG2 signal name to open the Signal Properties dialog.

•Type in MyColor into the Signal Type box. MyColor is the name of the user defined type that we will use.

•Press OK to close the dialog.

sig2_properties_dlg

•Double-click on the first waveform segment on SIG2 to open the Edit Bus State dialog.

•Enter some color value for each segment (we used RED, GREEN, BLUE).

•Click OK to close the dialog

sig2_waveform

•Your timing diagram should resemble the figure below.

diagram4-hdlStimulus-UDTvirtualStates