Congratulations, you have now completed the VHDL-Verilog Stimulus Tutorial. You have generated both a VHDL and a Verilog test bench using the Export > Export As menu function. You have investigated the language independent waveform state values and the signal data types. And you have used the Report window to view the generated code. For more information on the basic VHDL/Verilog generation please refer to the Timing Diagram Editor Manual Chapter 4: Simulated Signals and VHDL/Verilog Export.